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1 //===-- SparcAsmPrinter.cpp - Sparc LLVM assembly writer ------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to GAS-format SPARC assembly language.
12 //===----------------------------------------------------------------------===//
37 #define DEBUG_TYPE "asm-printer"
43 *OutStreamer->getTargetStreamer());
185 const MachineOperand &MO = MI->getOperand(0);
239 // <GET-PC> // This will be either `call <EndLabel>` or `rd %pc, %o7`.
241 // sethi %hi(_GLOBAL_OFFSET_TABLE_+(<SethiLabel>-<StartLabel>)), <MO>
243 // or <MO>, %lo(_GLOBAL_OFFSET_TABLE_+(<EndLabel>-<StartLabel>))), <MO>
246 OutStreamer->emitLabel(StartLabel);
255 // in non-leaf functions, so would this be worth the effort?)
258 OutStreamer->emitLabel(SethiLabel);
263 OutStreamer->emitLabel(EndLabel);
272 Sparc_MC::verifyInstructionPredicates(MI->getOpcode(),
275 switch (MI->getOpcode()) {
284 MachineBasicBlock::const_instr_iterator I = MI->getIterator();
285 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
290 } while ((++I != E) && I->isInsideBundle()); // Delay slot check.
294 if (!MF->getSubtarget<SparcSubtarget>().is64Bit())
297 const MachineRegisterInfo &MRI = MF->getRegInfo();
314 const MachineOperand &MO = MI->getOperand (opNum);
315 SparcMCExpr::VariantKind TF = (SparcMCExpr::VariantKind) MO.getTargetFlags();
317 bool CloseParen = SparcMCExpr::printVariantKind(O, TF);
328 MO.getMBB()->getSymbol()->print(O, MAI);
334 O << GetBlockAddressSymbol(MO.getBlockAddress())->getName();
344 MO.getMetadata()->printAsOperand(O, MMI->getModule());
363 if (MI->getOperand(opNum+1).isReg() &&
364 MI->getOperand(opNum+1).getReg() == SP::G0)
366 if (MI->getOperand(opNum+1).isImm() &&
367 MI->getOperand(opNum+1).getImm() == 0)
374 /// PrintAsmOperand - Print out an operand for an inline asm expression.
384 // See if this is a generic print operand
386 case 'L': // Low order register of a twin word register operand
387 case 'H': // High order register of a twin word register operand
389 const SparcSubtarget &Subtarget = MF->getSubtarget<SparcSubtarget>();
390 const MachineOperand &MO = MI->getOperand(OpNo);
396 // If we aren't given a register pair already, find out which pair it
398 // refers to the high part of the twinword, needs to be an even-numbered
400 MOReg = RegisterInfo->getMatchingSuperReg(MOReg, SP::sub_even,
405 Loc, "Hi part of pair should point to an even-numbered register");
414 HiReg = RegisterInfo->getSubReg(MOReg, SP::sub_even);
415 LoReg = RegisterInfo->getSubReg(MOReg, SP::sub_odd);