Lines Matching defs:Def
186 Register Def = MI.getOperand(0).getReg();
197 // Erase Def's assign type instruction if we are going to replace Def.
198 if (MachineInstr *AssignMI = findAssignTypeInstr(Def, MIB.getMRI()))
200 MIB.getMRI()->replaceRegWith(Def, Source);
202 GR->assignSPIRVTypeToVReg(AssignedPtrType, Def, MF);
203 MIB.buildBitcast(Def, Source);
256 if (SPIRVType *Def = propagateSPIRVType(DefInstr, GR, MRI, MIB)) {
257 unsigned CurrentBW = GR->getScalarOrVectorBitWidth(Def);
260 unsigned NumElements = GR->getScalarOrVectorComponentCount(Def);
279 MachineInstr *Def = Op.isReg() ? MRI.getVRegDef(Op.getReg()) : nullptr;
280 if (Def)
281 SpirvTy = propagateSPIRVType(Def, GR, MRI, MIB);
374 MachineInstr *Def = MRI.getVRegDef(Reg);
376 MIB.setInsertPt(*Def->getParent(),
377 (Def->getNextNode() ? Def->getNextNode()->getIterator()
378 : Def->getParent()->end()));
391 // Copy MIFlags from Def to ASSIGN_TYPE instruction. It's required to keep
393 const uint32_t Flags = Def->getFlags();
399 Def->getOperand(0).setReg(NewReg);
460 MachineInstr *Def = MRI.getVRegDef(Reg);
461 assert(Def && "Expecting an instruction that defines the register");
463 if (Def->getOpcode() != TargetOpcode::G_GLOBAL_VALUE &&
464 Def->getOpcode() != SPIRV::ASSIGN_TYPE)
471 MachineInstr *Def = MRI.getVRegDef(Reg);
472 assert(Def && "Expecting an instruction that defines the register");
474 if (Def->getOpcode() != TargetOpcode::G_GLOBAL_VALUE &&
475 Def->getOpcode() != SPIRV::ASSIGN_TYPE)