Lines Matching defs:SPIRV
20 #include "SPIRV.h"
38 static cl::list<SPIRV::Capability::Capability>
43 cl::values(clEnumValN(SPIRV::Capability::Shader, "Shader",
47 SmallSet<SPIRV::Capability::Capability, 4> S;
60 INITIALIZE_PASS(SPIRVModuleAnalysis, DEBUG_TYPE, "SPIRV module analysis", true,
73 static SPIRV::Requirements
74 getSymbolicOperandRequirements(SPIRV::OperandCategory::OperandCategory Category,
76 SPIRV::RequirementHandler &Reqs) {
120 if (llvm::all_of(ReqExts, [&ST](const SPIRV::Extension::Extension &Ext) {
134 for (int i = 0; i < SPIRV::NUM_MODULE_SECTIONS; i++)
147 MAI.Addr = static_cast<SPIRV::AddressingModel::AddressingModel>(
150 static_cast<SPIRV::MemoryModel::MemoryModel>(getMetadataUInt(MemMD, 1));
153 MAI.Mem = ST->isOpenCLEnv() ? SPIRV::MemoryModel::OpenCL
154 : SPIRV::MemoryModel::GLSL450;
155 if (MAI.Mem == SPIRV::MemoryModel::OpenCL) {
157 MAI.Addr = PtrSize == 32 ? SPIRV::AddressingModel::Physical32
158 : PtrSize == 64 ? SPIRV::AddressingModel::Physical64
159 : SPIRV::AddressingModel::Logical;
162 MAI.Addr = SPIRV::AddressingModel::Logical;
168 MAI.SrcLang = SPIRV::SourceLanguage::OpenCL_C;
169 // Construct version literal in accordance with SPIRV-LLVM-Translator.
182 // run-times with Unknown/0.0 version output. For a reference, LLVM-SPIRV
185 MAI.SrcLang = SPIRV::SourceLanguage::OpenCL_CPP;
188 MAI.SrcLang = SPIRV::SourceLanguage::Unknown;
205 MAI.Reqs.getAndAddRequirements(SPIRV::OperandCategory::MemoryModelOperand,
207 MAI.Reqs.getAndAddRequirements(SPIRV::OperandCategory::SourceLanguageOperand,
209 MAI.Reqs.getAndAddRequirements(SPIRV::OperandCategory::AddressingModelOperand,
215 SPIRV::InstructionSet::OpenCL_std)] =
222 SPIRV::ModuleAnalysisInfo *MAI,
223 SPIRV::ModuleSectionType MSType,
234 const std::vector<SPIRV::DTSortableEntry *> &DepsGraph,
235 SPIRV::ModuleSectionType MSType,
236 std::function<bool(const SPIRV::DTSortableEntry *)> Pred,
238 DenseSet<const SPIRV::DTSortableEntry *> Visited;
240 std::function<void(const SPIRV::DTSortableEntry *)> RecHoistUtil;
244 &RecHoistUtil](const SPIRV::DTSortableEntry *E) {
284 std::vector<SPIRV::DTSortableEntry *> DepsGraph;
289 DepsGraph, SPIRV::MB_TypeConstVars,
290 [](const SPIRV::DTSortableEntry *E) { return !E->getIsFunc(); });
299 if (MI.getOpcode() == SPIRV::OpExtension) {
301 auto Ext = SPIRV::Extension::Extension(MI.getOperand(0).getImm());
304 } else if (MI.getOpcode() == SPIRV::OpCapability) {
305 auto Cap = SPIRV::Capability::Capability(MI.getOperand(0).getImm());
314 DepsGraph, SPIRV::MB_ExtFuncDecls,
315 [](const SPIRV::DTSortableEntry *E) { return E->getIsFunc(); }, true);
324 if (MI.getOpcode() == SPIRV::OpDecorate) {
327 if (Dec == static_cast<unsigned>(SPIRV::Decoration::LinkageAttributes)) {
329 if (Lnk == static_cast<unsigned>(SPIRV::LinkageType::Import)) {
337 } else if (MI.getOpcode() == SPIRV::OpFunction) {
351 for (auto &MI : MAI.MS[SPIRV::MB_TypeConstVars])
352 if (MI->getOpcode() == SPIRV::OpConstantFunctionPointerINTEL)
360 assert(FunDefMI->getOpcode() == SPIRV::OpFunction &&
380 SPIRV::ModuleAnalysisInfo &MAI) {
401 static void collectOtherInstr(MachineInstr &MI, SPIRV::ModuleAnalysisInfo &MAI,
402 SPIRV::ModuleSectionType MSType, InstrTraces &IS,
430 if (OpCode == SPIRV::OpName || OpCode == SPIRV::OpMemberName) {
431 collectOtherInstr(MI, MAI, SPIRV::MB_DebugNames, IS);
432 } else if (OpCode == SPIRV::OpEntryPoint) {
433 collectOtherInstr(MI, MAI, SPIRV::MB_EntryPoints, IS);
435 collectOtherInstr(MI, MAI, SPIRV::MB_Annotations, IS);
440 collectOtherInstr(MI, MAI, SPIRV::MB_TypeConstVars, IS);
441 } else if (OpCode == SPIRV::OpFunction) {
443 } else if (OpCode == SPIRV::OpTypeForwardPointer) {
444 collectOtherInstr(MI, MAI, SPIRV::MB_TypeConstVars, IS, false);
470 if (MI.getOpcode() != SPIRV::OpExtInst)
481 void SPIRV::RequirementHandler::getAndAddRequirements(
482 SPIRV::OperandCategory::OperandCategory Category, uint32_t i,
487 void SPIRV::RequirementHandler::recursiveAddCapabilities(
497 void SPIRV::RequirementHandler::addCapabilities(const CapabilityList &ToAdd) {
509 void SPIRV::RequirementHandler::addRequirements(
510 const SPIRV::Requirements &Req) {
542 void SPIRV::RequirementHandler::checkSatisfiable(
597 void SPIRV::RequirementHandler::addAvailableCaps(const CapabilityList &ToAdd) {
601 SPIRV::OperandCategory::CapabilityOperand, Cap));
604 void SPIRV::RequirementHandler::removeCapabilityIf(
612 namespace SPIRV {
682 } // namespace SPIRV
688 SPIRV::RequirementHandler &Reqs,
691 auto Dec = static_cast<SPIRV::Decoration::Decoration>(DecOp);
693 SPIRV::OperandCategory::DecorationOperand, Dec, ST, Reqs));
695 if (Dec == SPIRV::Decoration::BuiltIn) {
697 auto BuiltIn = static_cast<SPIRV::BuiltIn::BuiltIn>(BuiltInOp);
699 SPIRV::OperandCategory::BuiltInOperand, BuiltIn, ST, Reqs));
700 } else if (Dec == SPIRV::Decoration::LinkageAttributes) {
702 SPIRV::LinkageType::LinkageType LnkType =
703 static_cast<SPIRV::LinkageType::LinkageType>(LinkageOp);
704 if (LnkType == SPIRV::LinkageType::LinkOnceODR)
705 Reqs.addExtension(SPIRV::Extension::SPV_KHR_linkonce_odr);
706 } else if (Dec == SPIRV::Decoration::CacheControlLoadINTEL ||
707 Dec == SPIRV::Decoration::CacheControlStoreINTEL) {
708 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_cache_controls);
709 } else if (Dec == SPIRV::Decoration::HostAccessINTEL) {
710 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_global_variable_host_access);
711 } else if (Dec == SPIRV::Decoration::InitModeINTEL ||
712 Dec == SPIRV::Decoration::ImplementInRegisterMapINTEL) {
714 SPIRV::Extension::SPV_INTEL_global_variable_fpga_decorations);
720 SPIRV::RequirementHandler &Reqs,
726 auto ImgFormat = static_cast<SPIRV::ImageFormat::ImageFormat>(ImgFormatOp);
727 Reqs.getAndAddRequirements(SPIRV::OperandCategory::ImageFormatOperand,
736 case SPIRV::Dim::DIM_1D:
737 Reqs.addRequirements(NoSampler ? SPIRV::Capability::Image1D
738 : SPIRV::Capability::Sampled1D);
740 case SPIRV::Dim::DIM_2D:
742 Reqs.addRequirements(SPIRV::Capability::ImageMSArray);
744 case SPIRV::Dim::DIM_Cube:
745 Reqs.addRequirements(SPIRV::Capability::Shader);
747 Reqs.addRequirements(NoSampler ? SPIRV::Capability::ImageCubeArray
748 : SPIRV::Capability::SampledCubeArray);
750 case SPIRV::Dim::DIM_Rect:
751 Reqs.addRequirements(NoSampler ? SPIRV::Capability::ImageRect
752 : SPIRV::Capability::SampledRect);
754 case SPIRV::Dim::DIM_Buffer:
755 Reqs.addRequirements(NoSampler ? SPIRV::Capability::ImageBuffer
756 : SPIRV::Capability::SampledBuffer);
758 case SPIRV::Dim::DIM_SubpassData:
759 Reqs.addRequirements(SPIRV::Capability::InputAttachment);
766 MI.getOperand(8).getImm() == SPIRV::AccessQualifier::ReadWrite)
767 Reqs.addRequirements(SPIRV::Capability::ImageReadWrite);
769 Reqs.addRequirements(SPIRV::Capability::ImageBasic);
777 SPIRV::RequirementHandler &Reqs,
783 if (TypeDef->getOpcode() != SPIRV::OpTypeFloat)
789 if (Op == SPIRV::OpAtomicFAddEXT) {
790 if (!ST.canUseExtension(SPIRV::Extension::SPV_EXT_shader_atomic_float_add))
792 Reqs.addExtension(SPIRV::Extension::SPV_EXT_shader_atomic_float_add);
796 SPIRV::Extension::SPV_EXT_shader_atomic_float16_add))
798 Reqs.addExtension(SPIRV::Extension::SPV_EXT_shader_atomic_float16_add);
799 Reqs.addCapability(SPIRV::Capability::AtomicFloat16AddEXT);
802 Reqs.addCapability(SPIRV::Capability::AtomicFloat32AddEXT);
805 Reqs.addCapability(SPIRV::Capability::AtomicFloat64AddEXT);
813 SPIRV::Extension::SPV_EXT_shader_atomic_float_min_max))
815 Reqs.addExtension(SPIRV::Extension::SPV_EXT_shader_atomic_float_min_max);
818 Reqs.addCapability(SPIRV::Capability::AtomicFloat16MinMaxEXT);
821 Reqs.addCapability(SPIRV::Capability::AtomicFloat32MinMaxEXT);
824 Reqs.addCapability(SPIRV::Capability::AtomicFloat64MinMaxEXT);
834 SPIRV::RequirementHandler &Reqs,
837 case SPIRV::OpMemoryModel: {
839 Reqs.getAndAddRequirements(SPIRV::OperandCategory::AddressingModelOperand,
842 Reqs.getAndAddRequirements(SPIRV::OperandCategory::MemoryModelOperand, Mem,
846 case SPIRV::OpEntryPoint: {
848 Reqs.getAndAddRequirements(SPIRV::OperandCategory::ExecutionModelOperand,
852 case SPIRV::OpExecutionMode:
853 case SPIRV::OpExecutionModeId: {
855 Reqs.getAndAddRequirements(SPIRV::OperandCategory::ExecutionModeOperand,
859 case SPIRV::OpTypeMatrix:
860 Reqs.addCapability(SPIRV::Capability::Matrix);
862 case SPIRV::OpTypeInt: {
865 Reqs.addCapability(SPIRV::Capability::Int64);
867 Reqs.addCapability(SPIRV::Capability::Int16);
869 Reqs.addCapability(SPIRV::Capability::Int8);
872 case SPIRV::OpTypeFloat: {
875 Reqs.addCapability(SPIRV::Capability::Float64);
877 Reqs.addCapability(SPIRV::Capability::Float16);
880 case SPIRV::OpTypeVector: {
883 Reqs.addCapability(SPIRV::Capability::Vector16);
886 case SPIRV::OpTypePointer: {
888 Reqs.getAndAddRequirements(SPIRV::OperandCategory::StorageClassOperand, SC,
897 if (TypeDef->getOpcode() == SPIRV::OpTypeFloat &&
899 Reqs.addCapability(SPIRV::Capability::Float16Buffer);
902 case SPIRV::OpBitReverse:
903 case SPIRV::OpBitFieldInsert:
904 case SPIRV::OpBitFieldSExtract:
905 case SPIRV::OpBitFieldUExtract:
906 if (!ST.canUseExtension(SPIRV::Extension::SPV_KHR_bit_instructions)) {
907 Reqs.addCapability(SPIRV::Capability::Shader);
910 Reqs.addExtension(SPIRV::Extension::SPV_KHR_bit_instructions);
911 Reqs.addCapability(SPIRV::Capability::BitInstructions);
913 case SPIRV::OpTypeRuntimeArray:
914 Reqs.addCapability(SPIRV::Capability::Shader);
916 case SPIRV::OpTypeOpaque:
917 case SPIRV::OpTypeEvent:
918 Reqs.addCapability(SPIRV::Capability::Kernel);
920 case SPIRV::OpTypePipe:
921 case SPIRV::OpTypeReserveId:
922 Reqs.addCapability(SPIRV::Capability::Pipes);
924 case SPIRV::OpTypeDeviceEvent:
925 case SPIRV::OpTypeQueue:
926 case SPIRV::OpBuildNDRange:
927 Reqs.addCapability(SPIRV::Capability::DeviceEnqueue);
929 case SPIRV::OpDecorate:
930 case SPIRV::OpDecorateId:
931 case SPIRV::OpDecorateString:
934 case SPIRV::OpMemberDecorate:
935 case SPIRV::OpMemberDecorateString:
938 case SPIRV::OpInBoundsPtrAccessChain:
939 Reqs.addCapability(SPIRV::Capability::Addresses);
941 case SPIRV::OpConstantSampler:
942 Reqs.addCapability(SPIRV::Capability::LiteralSampler);
944 case SPIRV::OpTypeImage:
947 case SPIRV::OpTypeSampler:
948 Reqs.addCapability(SPIRV::Capability::ImageBasic);
950 case SPIRV::OpTypeForwardPointer:
952 Reqs.addCapability(SPIRV::Capability::Addresses);
954 case SPIRV::OpAtomicFlagTestAndSet:
955 case SPIRV::OpAtomicLoad:
956 case SPIRV::OpAtomicStore:
957 case SPIRV::OpAtomicExchange:
958 case SPIRV::OpAtomicCompareExchange:
959 case SPIRV::OpAtomicIIncrement:
960 case SPIRV::OpAtomicIDecrement:
961 case SPIRV::OpAtomicIAdd:
962 case SPIRV::OpAtomicISub:
963 case SPIRV::OpAtomicUMin:
964 case SPIRV::OpAtomicUMax:
965 case SPIRV::OpAtomicSMin:
966 case SPIRV::OpAtomicSMax:
967 case SPIRV::OpAtomicAnd:
968 case SPIRV::OpAtomicOr:
969 case SPIRV::OpAtomicXor: {
972 if (MI.getOpcode() == SPIRV::OpAtomicStore) {
980 if (TypeDef->getOpcode() == SPIRV::OpTypeInt) {
983 Reqs.addCapability(SPIRV::Capability::Int64Atomics);
987 case SPIRV::OpGroupNonUniformIAdd:
988 case SPIRV::OpGroupNonUniformFAdd:
989 case SPIRV::OpGroupNonUniformIMul:
990 case SPIRV::OpGroupNonUniformFMul:
991 case SPIRV::OpGroupNonUniformSMin:
992 case SPIRV::OpGroupNonUniformUMin:
993 case SPIRV::OpGroupNonUniformFMin:
994 case SPIRV::OpGroupNonUniformSMax:
995 case SPIRV::OpGroupNonUniformUMax:
996 case SPIRV::OpGroupNonUniformFMax:
997 case SPIRV::OpGroupNonUniformBitwiseAnd:
998 case SPIRV::OpGroupNonUniformBitwiseOr:
999 case SPIRV::OpGroupNonUniformBitwiseXor:
1000 case SPIRV::OpGroupNonUniformLogicalAnd:
1001 case SPIRV::OpGroupNonUniformLogicalOr:
1002 case SPIRV::OpGroupNonUniformLogicalXor: {
1006 case SPIRV::GroupOperation::Reduce:
1007 case SPIRV::GroupOperation::InclusiveScan:
1008 case SPIRV::GroupOperation::ExclusiveScan:
1009 Reqs.addCapability(SPIRV::Capability::Kernel);
1010 Reqs.addCapability(SPIRV::Capability::GroupNonUniformArithmetic);
1011 Reqs.addCapability(SPIRV::Capability::GroupNonUniformBallot);
1013 case SPIRV::GroupOperation::ClusteredReduce:
1014 Reqs.addCapability(SPIRV::Capability::GroupNonUniformClustered);
1016 case SPIRV::GroupOperation::PartitionedReduceNV:
1017 case SPIRV::GroupOperation::PartitionedInclusiveScanNV:
1018 case SPIRV::GroupOperation::PartitionedExclusiveScanNV:
1019 Reqs.addCapability(SPIRV::Capability::GroupNonUniformPartitionedNV);
1024 case SPIRV::OpGroupNonUniformShuffle:
1025 case SPIRV::OpGroupNonUniformShuffleXor:
1026 Reqs.addCapability(SPIRV::Capability::GroupNonUniformShuffle);
1028 case SPIRV::OpGroupNonUniformShuffleUp:
1029 case SPIRV::OpGroupNonUniformShuffleDown:
1030 Reqs.addCapability(SPIRV::Capability::GroupNonUniformShuffleRelative);
1032 case SPIRV::OpGroupAll:
1033 case SPIRV::OpGroupAny:
1034 case SPIRV::OpGroupBroadcast:
1035 case SPIRV::OpGroupIAdd:
1036 case SPIRV::OpGroupFAdd:
1037 case SPIRV::OpGroupFMin:
1038 case SPIRV::OpGroupUMin:
1039 case SPIRV::OpGroupSMin:
1040 case SPIRV::OpGroupFMax:
1041 case SPIRV::OpGroupUMax:
1042 case SPIRV::OpGroupSMax:
1043 Reqs.addCapability(SPIRV::Capability::Groups);
1045 case SPIRV::OpGroupNonUniformElect:
1046 Reqs.addCapability(SPIRV::Capability::GroupNonUniform);
1048 case SPIRV::OpGroupNonUniformAll:
1049 case SPIRV::OpGroupNonUniformAny:
1050 case SPIRV::OpGroupNonUniformAllEqual:
1051 Reqs.addCapability(SPIRV::Capability::GroupNonUniformVote);
1053 case SPIRV::OpGroupNonUniformBroadcast:
1054 case SPIRV::OpGroupNonUniformBroadcastFirst:
1055 case SPIRV::OpGroupNonUniformBallot:
1056 case SPIRV::OpGroupNonUniformInverseBallot:
1057 case SPIRV::OpGroupNonUniformBallotBitExtract:
1058 case SPIRV::OpGroupNonUniformBallotBitCount:
1059 case SPIRV::OpGroupNonUniformBallotFindLSB:
1060 case SPIRV::OpGroupNonUniformBallotFindMSB:
1061 Reqs.addCapability(SPIRV::Capability::GroupNonUniformBallot);
1063 case SPIRV::OpSubgroupShuffleINTEL:
1064 case SPIRV::OpSubgroupShuffleDownINTEL:
1065 case SPIRV::OpSubgroupShuffleUpINTEL:
1066 case SPIRV::OpSubgroupShuffleXorINTEL:
1067 if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_subgroups)) {
1068 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_subgroups);
1069 Reqs.addCapability(SPIRV::Capability::SubgroupShuffleINTEL);
1072 case SPIRV::OpSubgroupBlockReadINTEL:
1073 case SPIRV::OpSubgroupBlockWriteINTEL:
1074 if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_subgroups)) {
1075 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_subgroups);
1076 Reqs.addCapability(SPIRV::Capability::SubgroupBufferBlockIOINTEL);
1079 case SPIRV::OpSubgroupImageBlockReadINTEL:
1080 case SPIRV::OpSubgroupImageBlockWriteINTEL:
1081 if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_subgroups)) {
1082 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_subgroups);
1083 Reqs.addCapability(SPIRV::Capability::SubgroupImageBlockIOINTEL);
1086 case SPIRV::OpAssumeTrueKHR:
1087 case SPIRV::OpExpectKHR:
1088 if (ST.canUseExtension(SPIRV::Extension::SPV_KHR_expect_assume)) {
1089 Reqs.addExtension(SPIRV::Extension::SPV_KHR_expect_assume);
1090 Reqs.addCapability(SPIRV::Capability::ExpectAssumeKHR);
1093 case SPIRV::OpPtrCastToCrossWorkgroupINTEL:
1094 case SPIRV::OpCrossWorkgroupCastToPtrINTEL:
1095 if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_usm_storage_classes)) {
1096 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_usm_storage_classes);
1097 Reqs.addCapability(SPIRV::Capability::USMStorageClassesINTEL);
1100 case SPIRV::OpConstantFunctionPointerINTEL:
1101 if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_function_pointers)) {
1102 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_function_pointers);
1103 Reqs.addCapability(SPIRV::Capability::FunctionPointersINTEL);
1106 case SPIRV::OpGroupNonUniformRotateKHR:
1107 if (!ST.canUseExtension(SPIRV::Extension::SPV_KHR_subgroup_rotate))
1111 Reqs.addExtension(SPIRV::Extension::SPV_KHR_subgroup_rotate);
1112 Reqs.addCapability(SPIRV::Capability::GroupNonUniformRotateKHR);
1113 Reqs.addCapability(SPIRV::Capability::GroupNonUniform);
1115 case SPIRV::OpGroupIMulKHR:
1116 case SPIRV::OpGroupFMulKHR:
1117 case SPIRV::OpGroupBitwiseAndKHR:
1118 case SPIRV::OpGroupBitwiseOrKHR:
1119 case SPIRV::OpGroupBitwiseXorKHR:
1120 case SPIRV::OpGroupLogicalAndKHR:
1121 case SPIRV::OpGroupLogicalOrKHR:
1122 case SPIRV::OpGroupLogicalXorKHR:
1124 SPIRV::Extension::SPV_KHR_uniform_group_instructions)) {
1125 Reqs.addExtension(SPIRV::Extension::SPV_KHR_uniform_group_instructions);
1126 Reqs.addCapability(SPIRV::Capability::GroupUniformArithmeticKHR);
1129 case SPIRV::OpReadClockKHR:
1130 if (!ST.canUseExtension(SPIRV::Extension::SPV_KHR_shader_clock))
1134 Reqs.addExtension(SPIRV::Extension::SPV_KHR_shader_clock);
1135 Reqs.addCapability(SPIRV::Capability::ShaderClockKHR);
1137 case SPIRV::OpFunctionPointerCallINTEL:
1138 if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_function_pointers)) {
1139 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_function_pointers);
1140 Reqs.addCapability(SPIRV::Capability::FunctionPointersINTEL);
1143 case SPIRV::OpAtomicFAddEXT:
1144 case SPIRV::OpAtomicFMinEXT:
1145 case SPIRV::OpAtomicFMaxEXT:
1148 case SPIRV::OpConvertBF16ToFINTEL:
1149 case SPIRV::OpConvertFToBF16INTEL:
1150 if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_bfloat16_conversion)) {
1151 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_bfloat16_conversion);
1152 Reqs.addCapability(SPIRV::Capability::BFloat16ConversionINTEL);
1155 case SPIRV::OpVariableLengthArrayINTEL:
1156 case SPIRV::OpSaveMemoryINTEL:
1157 case SPIRV::OpRestoreMemoryINTEL:
1158 if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_variable_length_array)) {
1159 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_variable_length_array);
1160 Reqs.addCapability(SPIRV::Capability::VariableLengthArrayINTEL);
1163 case SPIRV::OpAsmTargetINTEL:
1164 case SPIRV::OpAsmINTEL:
1165 case SPIRV::OpAsmCallINTEL:
1166 if (ST.canUseExtension(SPIRV::Extension::SPV_INTEL_inline_assembly)) {
1167 Reqs.addExtension(SPIRV::Extension::SPV_INTEL_inline_assembly);
1168 Reqs.addCapability(SPIRV::Capability::AsmINTEL);
1171 case SPIRV::OpTypeCooperativeMatrixKHR:
1172 if (!ST.canUseExtension(SPIRV::Extension::SPV_KHR_cooperative_matrix))
1177 Reqs.addExtension(SPIRV::Extension::SPV_KHR_cooperative_matrix);
1178 Reqs.addCapability(SPIRV::Capability::CooperativeMatrixKHR);
1187 Reqs.removeCapabilityIf(SPIRV::Capability::BitInstructions,
1188 SPIRV::Capability::Shader);
1191 static void collectReqs(const Module &M, SPIRV::ModuleAnalysisInfo &MAI,
1216 SPIRV::OperandCategory::ExecutionModeOperand, EM, ST);
1219 case SPIRV::ExecutionMode::DenormPreserve:
1220 case SPIRV::ExecutionMode::DenormFlushToZero:
1221 case SPIRV::ExecutionMode::SignedZeroInfNanPreserve:
1222 case SPIRV::ExecutionMode::RoundingModeRTE:
1223 case SPIRV::ExecutionMode::RoundingModeRTZ:
1231 ST.canUseExtension(SPIRV::Extension::SPV_KHR_float_controls))
1232 MAI.Reqs.addExtension(SPIRV::Extension::SPV_KHR_float_controls);
1240 SPIRV::OperandCategory::ExecutionModeOperand,
1241 SPIRV::ExecutionMode::LocalSize, ST);
1244 SPIRV::OperandCategory::ExecutionModeOperand,
1245 SPIRV::ExecutionMode::LocalSize, ST);
1249 SPIRV::OperandCategory::ExecutionModeOperand,
1250 SPIRV::ExecutionMode::LocalSizeHint, ST);
1253 SPIRV::OperandCategory::ExecutionModeOperand,
1254 SPIRV::ExecutionMode::SubgroupSize, ST);
1257 SPIRV::OperandCategory::ExecutionModeOperand,
1258 SPIRV::ExecutionMode::VecTypeHint, ST);
1261 ST.canUseExtension(SPIRV::Extension::SPV_INTEL_optnone)) {
1263 MAI.Reqs.addExtension(SPIRV::Extension::SPV_INTEL_optnone);
1264 MAI.Reqs.addCapability(SPIRV::Capability::OptNoneINTEL);
1270 unsigned Flags = SPIRV::FPFastMathMode::None;
1272 Flags |= SPIRV::FPFastMathMode::NotNaN;
1274 Flags |= SPIRV::FPFastMathMode::NotInf;
1276 Flags |= SPIRV::FPFastMathMode::NSZ;
1278 Flags |= SPIRV::FPFastMathMode::AllowRecip;
1280 Flags |= SPIRV::FPFastMathMode::Fast;
1286 SPIRV::RequirementHandler &Reqs) {
1288 getSymbolicOperandRequirements(SPIRV::OperandCategory::DecorationOperand,
1289 SPIRV::Decoration::NoSignedWrap, ST, Reqs)
1292 SPIRV::Decoration::NoSignedWrap, {});
1295 getSymbolicOperandRequirements(SPIRV::OperandCategory::DecorationOperand,
1296 SPIRV::Decoration::NoUnsignedWrap, ST,
1300 SPIRV::Decoration::NoUnsignedWrap, {});
1305 if (FMFlags == SPIRV::FPFastMathMode::None)
1308 buildOpDecorate(DstReg, I, TII, SPIRV::Decoration::FPFastMathMode, {FMFlags});
1314 SPIRV::ModuleAnalysisInfo &MAI) {
1325 struct SPIRV::ModuleAnalysisInfo SPIRVModuleAnalysis::MAI;
1362 if (MAI.MS[SPIRV::MB_EntryPoints].empty())
1363 MAI.Reqs.addCapability(SPIRV::Capability::Linkage);