Lines Matching defs:ResVReg
111 bool spvSelect(Register ResVReg, const SPIRVType *ResType,
114 bool selectGlobalValue(Register ResVReg, MachineInstr &I,
117 bool selectUnOpWithSrc(Register ResVReg, const SPIRVType *ResType,
120 bool selectUnOp(Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
123 bool selectBitcast(Register ResVReg, const SPIRVType *ResType,
126 bool selectLoad(Register ResVReg, const SPIRVType *ResType,
130 bool selectStackSave(Register ResVReg, const SPIRVType *ResType,
134 bool selectMemOperation(Register ResVReg, MachineInstr &I) const;
136 bool selectAtomicRMW(Register ResVReg, const SPIRVType *ResType,
140 bool selectAtomicCmpXchg(Register ResVReg, const SPIRVType *ResType,
145 bool selectAddrSpaceCast(Register ResVReg, const SPIRVType *ResType,
148 bool selectAnyOrAll(Register ResVReg, const SPIRVType *ResType,
151 bool selectAll(Register ResVReg, const SPIRVType *ResType,
154 bool selectAny(Register ResVReg, const SPIRVType *ResType,
157 bool selectBitreverse(Register ResVReg, const SPIRVType *ResType,
160 bool selectConstVector(Register ResVReg, const SPIRVType *ResType,
162 bool selectSplatVector(Register ResVReg, const SPIRVType *ResType,
165 bool selectCmp(Register ResVReg, const SPIRVType *ResType,
168 bool selectICmp(Register ResVReg, const SPIRVType *ResType,
170 bool selectFCmp(Register ResVReg, const SPIRVType *ResType,
173 bool selectFmix(Register ResVReg, const SPIRVType *ResType,
176 bool selectRsqrt(Register ResVReg, const SPIRVType *ResType,
184 bool selectConst(Register ResVReg, const SPIRVType *ResType, const APInt &Imm,
187 bool selectSelect(Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
189 bool selectIToF(Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
191 bool selectExt(Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
194 bool selectTrunc(Register ResVReg, const SPIRVType *ResType,
197 bool selectIntToBool(Register IntReg, Register ResVReg, MachineInstr &I,
200 bool selectOpUndef(Register ResVReg, const SPIRVType *ResType,
202 bool selectFreeze(Register ResVReg, const SPIRVType *ResType,
204 bool selectIntrinsic(Register ResVReg, const SPIRVType *ResType,
206 bool selectExtractVal(Register ResVReg, const SPIRVType *ResType,
208 bool selectInsertVal(Register ResVReg, const SPIRVType *ResType,
210 bool selectExtractElt(Register ResVReg, const SPIRVType *ResType,
212 bool selectInsertElt(Register ResVReg, const SPIRVType *ResType,
214 bool selectGEP(Register ResVReg, const SPIRVType *ResType,
217 bool selectFrameIndex(Register ResVReg, const SPIRVType *ResType,
219 bool selectAllocaArray(Register ResVReg, const SPIRVType *ResType,
225 bool selectPhi(Register ResVReg, const SPIRVType *ResType,
228 bool selectExtInst(Register ResVReg, const SPIRVType *ResType,
230 bool selectExtInst(Register ResVReg, const SPIRVType *ResType,
233 bool selectExtInst(Register ResVReg, const SPIRVType *ResType,
236 bool selectLog10(Register ResVReg, const SPIRVType *ResType,
239 bool selectSpvThreadId(Register ResVReg, const SPIRVType *ResType,
328 Register ResVReg = HasDefs ? I.getOperand(0).getReg() : Register(0);
329 SPIRVType *ResType = HasDefs ? GR.getSPIRVTypeForVReg(ResVReg) : nullptr;
331 if (spvSelect(ResVReg, ResType, I)) {
341 bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
349 return selectConst(ResVReg, ResType, I.getOperand(1).getCImm()->getValue(),
352 return selectGlobalValue(ResVReg, I);
354 return selectOpUndef(ResVReg, ResType, I);
356 return selectFreeze(ResVReg, ResType, I);
361 return selectIntrinsic(ResVReg, ResType, I);
363 return selectBitreverse(ResVReg, ResType, I);
366 return selectConstVector(ResVReg, ResType, I);
368 return selectSplatVector(ResVReg, ResType, I);
373 .addDef(ResVReg)
384 return selectMemOperation(ResVReg, I);
387 return selectICmp(ResVReg, ResType, I);
389 return selectFCmp(ResVReg, ResType, I);
392 return selectFrameIndex(ResVReg, ResType, I);
395 return selectLoad(ResVReg, ResType, I);
405 return selectPhi(ResVReg, ResType, I);
408 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertFToS);
410 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertFToU);
413 return selectIToF(ResVReg, ResType, I, true, SPIRV::OpConvertSToF);
415 return selectIToF(ResVReg, ResType, I, false, SPIRV::OpConvertUToF);
418 return selectUnOp(ResVReg, ResType, I, SPIRV::OpBitCount);
420 return selectExtInst(ResVReg, ResType, I, CL::s_min, GL::SMin);
422 return selectExtInst(ResVReg, ResType, I, CL::u_min, GL::UMin);
425 return selectExtInst(ResVReg, ResType, I, CL::s_max, GL::SMax);
427 return selectExtInst(ResVReg, ResType, I, CL::u_max, GL::UMax);
430 return selectExtInst(ResVReg, ResType, I, CL::fma, GL::Fma);
433 return selectExtInst(ResVReg, ResType, I, CL::pow, GL::Pow);
435 return selectExtInst(ResVReg, ResType, I, CL::pown);
438 return selectExtInst(ResVReg, ResType, I, CL::exp, GL::Exp);
440 return selectExtInst(ResVReg, ResType, I, CL::exp2, GL::Exp2);
443 return selectExtInst(ResVReg, ResType, I, CL::log, GL::Log);
445 return selectExtInst(ResVReg, ResType, I, CL::log2, GL::Log2);
447 return selectLog10(ResVReg, ResType, I);
450 return selectExtInst(ResVReg, ResType, I, CL::fabs, GL::FAbs);
452 return selectExtInst(ResVReg, ResType, I, CL::s_abs, GL::SAbs);
456 return selectExtInst(ResVReg, ResType, I, CL::fmin, GL::NMin);
459 return selectExtInst(ResVReg, ResType, I, CL::fmax, GL::NMax);
462 return selectExtInst(ResVReg, ResType, I, CL::copysign);
465 return selectExtInst(ResVReg, ResType, I, CL::ceil, GL::Ceil);
467 return selectExtInst(ResVReg, ResType, I, CL::floor, GL::Floor);
470 return selectExtInst(ResVReg, ResType, I, CL::cos, GL::Cos);
472 return selectExtInst(ResVReg, ResType, I, CL::sin, GL::Sin);
474 return selectExtInst(ResVReg, ResType, I, CL::tan, GL::Tan);
476 return selectExtInst(ResVReg, ResType, I, CL::acos, GL::Acos);
478 return selectExtInst(ResVReg, ResType, I, CL::asin, GL::Asin);
480 return selectExtInst(ResVReg, ResType, I, CL::atan, GL::Atan);
482 return selectExtInst(ResVReg, ResType, I, CL::cosh, GL::Cosh);
484 return selectExtInst(ResVReg, ResType, I, CL::sinh, GL::Sinh);
486 return selectExtInst(ResVReg, ResType, I, CL::tanh, GL::Tanh);
489 return selectExtInst(ResVReg, ResType, I, CL::sqrt, GL::Sqrt);
493 return selectExtInst(ResVReg, ResType, I, CL::ctz);
496 return selectExtInst(ResVReg, ResType, I, CL::clz);
499 return selectExtInst(ResVReg, ResType, I, CL::round, GL::Round);
501 return selectExtInst(ResVReg, ResType, I, CL::rint, GL::RoundEven);
503 return selectExtInst(ResVReg, ResType, I, CL::trunc, GL::Trunc);
506 return selectExtInst(ResVReg, ResType, I, CL::rint, GL::RoundEven);
509 return selectExtInst(ResVReg, ResType, I, CL::s_mul_hi);
511 return selectExtInst(ResVReg, ResType, I, CL::u_mul_hi);
514 return selectExtInst(ResVReg, ResType, I, CL::s_add_sat);
516 return selectExtInst(ResVReg, ResType, I, CL::u_add_sat);
518 return selectExtInst(ResVReg, ResType, I, CL::s_sub_sat);
520 return selectExtInst(ResVReg, ResType, I, CL::u_sub_sat);
523 return selectExt(ResVReg, ResType, I, true);
526 return selectExt(ResVReg, ResType, I, false);
528 return selectTrunc(ResVReg, ResType, I);
531 return selectUnOp(ResVReg, ResType, I, SPIRV::OpFConvert);
534 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertPtrToU);
536 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertUToPtr);
538 return selectBitcast(ResVReg, ResType, I);
540 return selectAddrSpaceCast(ResVReg, ResType, I);
557 .addDef(ResVReg)
568 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicOr);
570 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicIAdd);
572 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicAnd);
574 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicSMax);
576 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicSMin);
578 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicISub);
580 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicXor);
582 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicUMax);
584 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicUMin);
586 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicExchange);
588 return selectAtomicCmpXchg(ResVReg, ResType, I);
591 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFAddEXT);
594 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFAddEXT,
597 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFMinEXT);
599 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicFMaxEXT);
605 return selectStackSave(ResVReg, ResType, I);
617 bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
621 return selectExtInst(ResVReg, ResType, I,
625 bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
632 return selectExtInst(ResVReg, ResType, I, ExtInsts);
635 bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
646 .addDef(ResVReg)
659 bool SPIRVInstructionSelector::selectUnOpWithSrc(Register ResVReg,
665 .addDef(ResVReg)
671 bool SPIRVInstructionSelector::selectUnOp(Register ResVReg,
699 .addDef(ResVReg)
706 return selectUnOpWithSrc(ResVReg, ResType, I, I.getOperand(1).getReg(),
710 bool SPIRVInstructionSelector::selectBitcast(Register ResVReg,
717 return selectUnOp(ResVReg, ResType, I, SPIRV::OpBitcast);
771 bool SPIRVInstructionSelector::selectLoad(Register ResVReg,
777 .addDef(ResVReg)
810 bool SPIRVInstructionSelector::selectStackSave(Register ResVReg,
820 .addDef(ResVReg)
839 bool SPIRVInstructionSelector::selectMemOperation(Register ResVReg,
882 if (ResVReg.isValid() && ResVReg != MIB->getOperand(0).getReg())
883 BuildMI(BB, I, I.getDebugLoc(), TII.get(TargetOpcode::COPY), ResVReg)
888 bool SPIRVInstructionSelector::selectAtomicRMW(Register ResVReg,
917 .addDef(ResVReg)
942 Register ResVReg = I.getOperand(i).getReg();
943 SPIRVType *ResType = GR.getSPIRVTypeForVReg(ResVReg);
947 MRI->setRegClass(ResVReg, &SPIRV::IDRegClass);
948 MRI->setType(ResVReg, LLT::scalar(GR.getScalarOrVectorBitWidth(ResType)));
949 GR.assignSPIRVTypeToVReg(ResType, ResVReg, *GR.CurMF);
953 .addDef(ResVReg)
976 bool SPIRVInstructionSelector::selectAtomicCmpXchg(Register ResVReg,
1038 .addDef(ResVReg)
1073 bool SPIRVInstructionSelector::selectAddrSpaceCast(Register ResVReg,
1078 auto UIs = MRI->use_instructions(ResVReg);
1090 .addDef(ResVReg)
1100 SPIRV::StorageClass::StorageClass DstSC = GR.getPointerStorageClass(ResVReg);
1106 .addDef(ResVReg)
1112 return selectUnOp(ResVReg, ResType, I, SPIRV::OpPtrCastToGeneric);
1115 return selectUnOp(ResVReg, ResType, I, SPIRV::OpGenericCastToPtr);
1129 .addDef(ResVReg)
1138 return selectUnOp(ResVReg, ResType, I,
1141 return selectUnOp(ResVReg, ResType, I,
1144 return selectUnOp(ResVReg, ResType, I, SPIRV::OpPtrCastToGeneric);
1146 return selectUnOp(ResVReg, ResType, I, SPIRV::OpGenericCastToPtr);
1240 bool SPIRVInstructionSelector::selectAnyOrAll(Register ResVReg,
1256 assert(ResVReg == I.getOperand(0).getReg());
1259 .addDef(ResVReg)
1269 Register NotEqualReg = ResVReg;
1294 .addDef(ResVReg)
1300 bool SPIRVInstructionSelector::selectAll(Register ResVReg,
1303 return selectAnyOrAll(ResVReg, ResType, I, SPIRV::OpAll);
1306 bool SPIRVInstructionSelector::selectAny(Register ResVReg,
1309 return selectAnyOrAll(ResVReg, ResType, I, SPIRV::OpAny);
1312 bool SPIRVInstructionSelector::selectFmix(Register ResVReg,
1323 .addDef(ResVReg)
1333 bool SPIRVInstructionSelector::selectRsqrt(Register ResVReg,
1342 .addDef(ResVReg)
1350 bool SPIRVInstructionSelector::selectBitreverse(Register ResVReg,
1355 .addDef(ResVReg)
1361 bool SPIRVInstructionSelector::selectFreeze(Register ResVReg,
1401 bool SPIRVInstructionSelector::selectConstVector(Register ResVReg,
1423 .addDef(ResVReg)
1495 bool SPIRVInstructionSelector::selectSplatVector(Register ResVReg,
1521 .addDef(ResVReg)
1528 bool SPIRVInstructionSelector::selectCmp(Register ResVReg,
1538 .addDef(ResVReg)
1545 bool SPIRVInstructionSelector::selectICmp(Register ResVReg,
1558 return selectCmp(ResVReg, ResType, CmpOpc, I);
1607 bool SPIRVInstructionSelector::selectFCmp(Register ResVReg,
1611 return selectCmp(ResVReg, ResType, CmpOp, I);
1658 bool SPIRVInstructionSelector::selectSelect(Register ResVReg,
1670 .addDef(ResVReg)
1678 bool SPIRVInstructionSelector::selectIToF(Register ResVReg,
1695 return selectUnOpWithSrc(ResVReg, ResType, I, SrcReg, Opcode);
1698 bool SPIRVInstructionSelector::selectExt(Register ResVReg,
1703 return selectSelect(ResVReg, ResType, I, IsSigned);
1709 .addDef(ResVReg)
1714 return selectUnOp(ResVReg, ResType, I, Opcode);
1718 Register ResVReg,
1736 .addDef(ResVReg)
1743 bool SPIRVInstructionSelector::selectTrunc(Register ResVReg,
1748 if (GR.isScalarOrVectorOfType(ResVReg, SPIRV::OpTypeBool))
1749 return selectIntToBool(IntReg, ResVReg, I, ArgType, ResType);
1753 .addDef(ResVReg)
1758 return selectUnOp(ResVReg, ResType, I, Opcode);
1761 bool SPIRVInstructionSelector::selectConst(Register ResVReg,
1771 .addDef(ResVReg)
1777 if (Reg == ResVReg)
1780 .addDef(ResVReg)
1785 .addDef(ResVReg)
1793 bool SPIRVInstructionSelector::selectOpUndef(Register ResVReg,
1797 .addDef(ResVReg)
1822 bool SPIRVInstructionSelector::selectInsertVal(Register ResVReg,
1827 .addDef(ResVReg)
1838 bool SPIRVInstructionSelector::selectExtractVal(Register ResVReg,
1843 .addDef(ResVReg)
1851 bool SPIRVInstructionSelector::selectInsertElt(Register ResVReg,
1855 return selectInsertVal(ResVReg, ResType, I);
1858 .addDef(ResVReg)
1866 bool SPIRVInstructionSelector::selectExtractElt(Register ResVReg,
1870 return selectExtractVal(ResVReg, ResType, I);
1873 .addDef(ResVReg)
1880 bool SPIRVInstructionSelector::selectGEP(Register ResVReg,
1895 .addDef(ResVReg)
1953 bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
1960 return selectLoad(ResVReg, ResType, I);
1964 return selectExtractVal(ResVReg, ResType, I);
1966 return selectInsertVal(ResVReg, ResType, I);
1968 return selectExtractElt(ResVReg, ResType, I);
1970 return selectInsertElt(ResVReg, ResType, I);
1972 return selectGEP(ResVReg, ResType, I);
1984 .addDef(ResVReg)
2000 .addDef(ResVReg)
2033 return selectAtomicCmpXchg(ResVReg, ResType, I);
2038 return selectFrameIndex(ResVReg, ResType, I);
2040 return selectAllocaArray(ResVReg, ResType, I);
2049 .addDef(ResVReg)
2055 return selectSpvThreadId(ResVReg, ResType, I);
2057 return selectAll(ResVReg, ResType, I);
2059 return selectAny(ResVReg, ResType, I);
2061 return selectFmix(ResVReg, ResType, I);
2063 return selectRsqrt(ResVReg, ResType, I);
2087 bool SPIRVInstructionSelector::selectAllocaArray(Register ResVReg,
2095 .addDef(ResVReg)
2101 bool SPIRVInstructionSelector::selectFrameIndex(Register ResVReg,
2122 .addDef(ResVReg)
2174 bool SPIRVInstructionSelector::selectPhi(Register ResVReg,
2178 .addDef(ResVReg)
2189 Register ResVReg, MachineInstr &I, const MachineInstr *Init) const {
2234 Register NewReg = ResVReg;
2262 assert(NewReg != ResVReg);
2264 .addDef(ResVReg)
2291 Register Reg = GR.buildGlobalVariable(ResVReg, ResType, GlobalIdent, GV,
2297 bool SPIRVInstructionSelector::selectLog10(Register ResVReg,
2301 return selectExtInst(ResVReg, ResType, I, CL::log10);
2339 .addDef(ResVReg)
2348 bool SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
2403 .addDef(ResVReg)