Lines Matching full:arguments
48 const SmallVectorImpl<Register> &Arguments;
52 const SmallVectorImpl<Register> &Arguments)
55 Arguments(Arguments) {}
182 // Extract the builtin function name and types of arguments from the call
224 const SmallVectorImpl<Register> &Arguments) {
237 BuiltinName, Builtin, ReturnRegister, ReturnType, Arguments);
280 BuiltinName, Builtin, ReturnRegister, ReturnType, Arguments);
311 BuiltinName, Builtin, ReturnRegister, ReturnType, Arguments);
582 unsigned Sz = Call->Arguments.size() - ImmArgs.size();
584 Register ArgReg = Call->Arguments[i];
600 assert(Call->Arguments.size() == 2 &&
601 "Need 2 arguments for atomic init translation");
602 MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
603 MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
605 .addUse(Call->Arguments[0])
606 .addUse(Call->Arguments[1]);
618 Register PtrRegister = Call->Arguments[0];
624 if (Call->Arguments.size() > 1) {
625 ScopeRegister = Call->Arguments[1];
631 if (Call->Arguments.size() > 2) {
633 MemSemanticsReg = Call->Arguments[2];
660 Register PtrRegister = Call->Arguments[0];
666 MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
671 .addUse(Call->Arguments[1]);
686 Register ObjectPtr = Call->Arguments[0]; // Pointer (volatile A *object.)
687 Register ExpectedArg = Call->Arguments[1]; // Comparator (C* expected).
688 Register Desired = Call->Arguments[2]; // Value (C Desired).
719 if (Call->Arguments.size() >= 4) {
720 assert(Call->Arguments.size() >= 5 &&
723 static_cast<std::memory_order>(getIConstVal(Call->Arguments[3], MRI));
725 static_cast<std::memory_order>(getIConstVal(Call->Arguments[4], MRI));
729 MemSemEqualReg = Call->Arguments[3];
731 MemSemUnequalReg = Call->Arguments[4];
732 MRI->setRegClass(Call->Arguments[3], &SPIRV::IDRegClass);
733 MRI->setRegClass(Call->Arguments[4], &SPIRV::IDRegClass);
742 if (Call->Arguments.size() >= 6) {
743 assert(Call->Arguments.size() == 6 &&
746 getIConstVal(Call->Arguments[5], MRI));
749 ScopeReg = Call->Arguments[5];
750 MRI->setRegClass(Call->Arguments[5], &SPIRV::IDRegClass);
793 Call->Arguments.size() >= 4 ? Call->Arguments[3] : Register();
795 assert(Call->Arguments.size() <= 4 &&
800 Register PtrRegister = Call->Arguments[0];
804 Call->Arguments.size() >= 3 ? Call->Arguments[2] : Register();
807 MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
808 Register ValueReg = Call->Arguments[1];
846 assert(Call->Arguments.size() == 4 &&
851 Register PtrReg = Call->Arguments[0];
854 Register ScopeReg = Call->Arguments[1];
857 Register MemSemanticsReg = Call->Arguments[2];
860 Register ValueReg = Call->Arguments[3];
885 Register PtrRegister = Call->Arguments[0];
888 Call->Arguments.size() >= 2 ? Call->Arguments[1] : Register();
898 Call->Arguments.size() >= 3 ? Call->Arguments[2] : Register();
919 unsigned MemFlags = getIConstVal(Call->Arguments[0], MRI);
933 static_cast<std::memory_order>(getIConstVal(Call->Arguments[1], MRI));
941 MemSemanticsReg = Call->Arguments[0];
949 if (Call->Arguments.size() >= 2) {
951 ((Opcode != SPIRV::OpMemoryBarrier && Call->Arguments.size() == 2) ||
952 (Opcode == SPIRV::OpMemoryBarrier && Call->Arguments.size() == 3)) &&
954 Register ScopeArg = (Opcode == SPIRV::OpMemoryBarrier) ? Call->Arguments[2]
955 : Call->Arguments[1];
964 ScopeReg = Call->Arguments[1];
1024 for (auto Argument : Call->Arguments)
1047 for (auto Argument : Call->Arguments)
1069 Register GroupOpReg = Call->Arguments[1];
1075 Register ScopeReg = Call->Arguments[0];
1083 for (unsigned i = 2; i < Call->Arguments.size(); ++i) {
1084 Register ArgReg = Call->Arguments[i];
1094 Register ConstRegister = Call->Arguments[0];
1100 if (GR->getSPIRVTypeForVReg(Call->Arguments[0])->getOpcode() !=
1132 if (Call->Arguments.size() > 0) {
1133 MIB.addUse(Arg0.isValid() ? Arg0 : Call->Arguments[0]);
1134 MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
1135 for (unsigned i = 1; i < Call->Arguments.size(); i++) {
1136 MIB.addUse(Call->Arguments[i]);
1137 MRI->setRegClass(Call->Arguments[i], &SPIRV::IDRegClass);
1174 // Minimal number or arguments set in TableGen records is 1
1175 if (SPIRVType *Arg0Type = GR->getSPIRVTypeForVReg(Call->Arguments[0])) {
1209 for (size_t i = 0; i < Call->Arguments.size(); ++i) {
1210 MIB.addUse(Call->Arguments[i]);
1211 MRI->setRegClass(Call->Arguments[i], &SPIRV::IDRegClass);
1238 Register ScopeReg = Call->Arguments[0];
1242 Register ConstGroupOpReg = Call->Arguments[1];
1255 Register ValueReg = Call->Arguments[2];
1332 Register IndexRegister = Call->Arguments[0];
1520 .addUse(Call->Arguments[0]);
1530 unsigned Opcode = GR->getSPIRVTypeForVReg(Call->Arguments[0])->getOpcode();
1536 .addUse(Call->Arguments[0])
1537 .addUse(Call->Arguments[1]);
1584 SPIRVType *ImgType = GR->getSPIRVTypeForVReg(Call->Arguments[0]);
1600 MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
1604 .addUse(Call->Arguments[0]);
1655 Register Image = Call->Arguments[0];
1718 Register Image = Call->Arguments[0];
1721 MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
1725 MRI->setRegClass(Call->Arguments[2], &SPIRV::IDRegClass);
1727 Register Sampler = Call->Arguments[1];
1767 .addUse(Call->Arguments[2]) // Coordinate.
1782 .addUse(Call->Arguments[1]) // Coordinate.
1784 .addUse(Call->Arguments[2]);
1790 .addUse(Call->Arguments[1]); // Coordinate.
1798 MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
1799 MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
1800 MIRBuilder.getMRI()->setRegClass(Call->Arguments[2], &SPIRV::IDRegClass);
1802 .addUse(Call->Arguments[0]) // Image.
1803 .addUse(Call->Arguments[1]) // Coordinate.
1804 .addUse(Call->Arguments[2]); // Texel.
1816 uint64_t Bitmask = getIConstVal(Call->Arguments[0], MRI);
1824 Register Image = Call->Arguments[0];
1836 .addUse(Call->Arguments[1]); // Sampler.
1855 MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
1856 MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
1857 MRI->setRegClass(Call->Arguments[3], &SPIRV::IDRegClass);
1862 .addUse(Call->Arguments[0]) // Image.
1863 .addUse(Call->Arguments[1]) // Coordinate.
1865 .addUse(Call->Arguments[3]);
1873 MIRBuilder.buildSelect(Call->ReturnRegister, Call->Arguments[0],
1874 Call->Arguments[1], Call->Arguments[2]);
1892 unsigned ArgSz = Call->Arguments.size();
1901 ImmArgs.push_back(getConstFromIntrinsic(Call->Arguments[LiteralIdx], MRI));
1904 SPIRVType *CoopMatrType = GR->getSPIRVTypeForVReg(Call->Arguments[0]);
1930 static_cast<unsigned>(getIConstVal(Call->Arguments[0], MRI));
1934 Register ConstRegister = Call->Arguments[1];
1964 for (unsigned i = 0; i < Call->Arguments.size(); i++)
1965 MIB.addUse(Call->Arguments[i]);
1977 MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
1978 SPIRVType *PtrType = GR->getSPIRVTypeForVReg(Call->Arguments[0]);
1987 // three other arguments, so pass zero constant on absence.
1988 unsigned NumArgs = Call->Arguments.size();
1990 Register GlobalWorkSize = Call->Arguments[NumArgs < 4 ? 1 : 2];
1993 NumArgs == 2 ? Register(0) : Call->Arguments[NumArgs < 4 ? 2 : 3];
1996 Register GlobalWorkOffset = NumArgs <= 3 ? Register(0) : Call->Arguments[1];
2041 .addUse(Call->Arguments[0])
2071 // Local sizes arguments: Sizes of block invoke arguments. Clang generates
2076 Register GepReg = Call->Arguments[LocalSizeArrayIdx];
2105 // SPIRV OpEnqueueKernel instruction has 10+ arguments.
2110 // Copy all arguments before block invoke function pointer.
2113 MIB.addUse(Call->Arguments[i]);
2115 // If there are no event arguments in the original call, add dummy ones.
2124 MachineInstr *BlockMI = getBlockStructInstr(Call->Arguments[BlockFIdx], MRI);
2129 Register BlockLiteralReg = Call->Arguments[BlockFIdx + 1];
2157 MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
2158 return MIRBuilder.buildInstr(Opcode).addUse(Call->Arguments[0]);
2165 MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
2169 .addUse(Call->Arguments[0]);
2171 MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
2172 MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
2174 .addUse(Call->Arguments[0])
2175 .addUse(Call->Arguments[1]);
2177 MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
2178 MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
2179 MIRBuilder.getMRI()->setRegClass(Call->Arguments[2], &SPIRV::IDRegClass);
2181 .addUse(Call->Arguments[0])
2182 .addUse(Call->Arguments[1])
2183 .addUse(Call->Arguments[2]);
2216 unsigned NumArgs = Call->Arguments.size();
2217 Register EventReg = Call->Arguments[NumArgs - 1];
2222 .addUse(Call->Arguments[0])
2223 .addUse(Call->Arguments[1])
2224 .addUse(Call->Arguments[2])
2225 .addUse(Call->Arguments.size() > 4
2226 ? Call->Arguments[3]
2237 .addUse(Call->Arguments[0])
2238 .addUse(Call->Arguments[1]);
2271 if (GR->isScalarOrVectorOfType(Call->Arguments[0], SPIRV::OpTypeInt)) {
2291 GR->getScalarOrVectorComponentCount(Call->Arguments[0]) ==
2300 } else if (GR->isScalarOrVectorOfType(Call->Arguments[0],
2312 GR->getScalarOrVectorComponentCount(Call->Arguments[0]) ==
2345 .addUse(Call->Arguments[0]);
2363 for (auto Argument : Call->Arguments)
2390 MIB.addUse(Call->Arguments[0]);
2392 MRI->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
2395 MIB.addUse(Call->Arguments[1]);
2396 MRI->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
2399 unsigned NumArgs = Call->Arguments.size();
2401 MIB.addImm(getConstFromIntrinsic(Call->Arguments[IsLoad ? 1 : 2], MRI));
2402 MRI->setRegClass(Call->Arguments[IsLoad ? 1 : 2], &SPIRV::IDRegClass);
2405 MIB.addImm(getConstFromIntrinsic(Call->Arguments[IsLoad ? 2 : 3], MRI));
2406 MRI->setRegClass(Call->Arguments[IsLoad ? 2 : 3], &SPIRV::IDRegClass);
2517 "Too few arguments to generate the builtin");
2519 LLVM_DEBUG(dbgs() << "More arguments provided than required!\n");