Lines Matching defs:MIRBuilder
393 buildBoolRegister(MachineIRBuilder &MIRBuilder, const SPIRVType *ResultType,
396 SPIRVType *BoolType = GR->getOrCreateSPIRVBoolType(MIRBuilder);
401 GR->getOrCreateSPIRVVectorType(BoolType, VectorElements, MIRBuilder);
410 MIRBuilder.getMRI()->createGenericVirtualRegister(Type);
411 MIRBuilder.getMRI()->setRegClass(ResultRegister, &SPIRV::IDRegClass);
412 GR->assignSPIRVTypeToVReg(BoolType, ResultRegister, MIRBuilder.getMF());
418 static bool buildSelectInst(MachineIRBuilder &MIRBuilder,
427 TrueConst = GR->getOrCreateConsIntVector(AllOnes, MIRBuilder, ReturnType);
428 FalseConst = GR->getOrCreateConsIntVector(0, MIRBuilder, ReturnType);
430 TrueConst = GR->buildConstantInt(1, MIRBuilder, ReturnType);
431 FalseConst = GR->buildConstantInt(0, MIRBuilder, ReturnType);
433 return MIRBuilder.buildSelect(ReturnRegister, SourceRegister, TrueConst,
440 MachineIRBuilder &MIRBuilder,
443 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
447 GR->assignSPIRVTypeToVReg(BaseType, DestinationReg, MIRBuilder.getMF());
452 MIRBuilder.buildLoad(DestinationReg, PtrRegister, PtrInfo, Align());
459 MachineIRBuilder &MIRBuilder, SPIRVType *VariableType,
463 MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass);
464 MIRBuilder.getMRI()->setType(NewRegister,
467 VariableType, MIRBuilder, SPIRV::StorageClass::Input);
468 GR->assignSPIRVTypeToVReg(PtrType, NewRegister, MIRBuilder.getMF());
474 /* HasLinkageTy */ hasLinkageTy, SPIRV::LinkageType::Import, MIRBuilder,
479 buildLoadInst(VariableType, Variable, MIRBuilder, GR, LLType, Reg);
480 MIRBuilder.getMRI()->setType(LoadedRegister, LLType);
529 static Register buildConstantIntReg(uint64_t Val, MachineIRBuilder &MIRBuilder,
532 SPIRVType *IntType = GR->getOrCreateSPIRVIntegerType(BitWidth, MIRBuilder);
533 return GR->buildConstantInt(Val, MIRBuilder, IntType);
538 MachineIRBuilder &MIRBuilder,
551 return buildConstantIntReg(Scope, MIRBuilder, GR);
556 MachineIRBuilder &MIRBuilder,
559 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
571 return buildConstantIntReg(Semantics, MIRBuilder, GR);
574 static bool buildOpFromWrapper(MachineIRBuilder &MIRBuilder, unsigned Opcode,
578 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
579 auto MIB = MIRBuilder.buildInstr(Opcode);
596 MachineIRBuilder &MIRBuilder) {
598 return buildOpFromWrapper(MIRBuilder, SPIRV::OpStore, Call, Register(0));
602 MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
603 MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
604 MIRBuilder.buildInstr(SPIRV::OpStore)
612 MachineIRBuilder &MIRBuilder,
616 return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicLoad, Call, TypeReg);
619 MIRBuilder.getMRI()->setRegClass(PtrRegister, &SPIRV::IDRegClass);
626 MIRBuilder.getMRI()->setRegClass(ScopeRegister, &SPIRV::IDRegClass);
628 ScopeRegister = buildConstantIntReg(SPIRV::Scope::Device, MIRBuilder, GR);
634 MIRBuilder.getMRI()->setRegClass(MemSemanticsReg, &SPIRV::IDRegClass);
639 MemSemanticsReg = buildConstantIntReg(Semantics, MIRBuilder, GR);
642 MIRBuilder.buildInstr(SPIRV::OpAtomicLoad)
653 MachineIRBuilder &MIRBuilder,
656 return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicStore, Call, Register(0));
659 buildConstantIntReg(SPIRV::Scope::Device, MIRBuilder, GR);
661 MIRBuilder.getMRI()->setRegClass(PtrRegister, &SPIRV::IDRegClass);
665 Register MemSemanticsReg = buildConstantIntReg(Semantics, MIRBuilder, GR);
666 MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
667 MIRBuilder.buildInstr(SPIRV::OpAtomicStore)
678 unsigned Opcode, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR) {
680 return buildOpFromWrapper(MIRBuilder, Opcode, Call,
684 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
736 MemSemEqualReg = buildConstantIntReg(MemSemEqual, MIRBuilder, GR);
738 MemSemUnequalReg = buildConstantIntReg(MemSemUnequal, MIRBuilder, GR);
753 ScopeReg = buildConstantIntReg(Scope, MIRBuilder, GR);
757 : buildLoadInst(SpvDesiredTy, ExpectedArg, MIRBuilder,
764 GR->assignSPIRVTypeToVReg(SpvDesiredTy, Tmp, MIRBuilder.getMF());
766 SPIRVType *IntTy = GR->getOrCreateSPIRVIntegerType(32, MIRBuilder);
767 MIRBuilder.buildInstr(Opcode)
777 MIRBuilder.buildInstr(SPIRV::OpStore).addUse(ExpectedArg).addUse(Tmp);
778 MIRBuilder.buildICmp(CmpInst::ICMP_EQ, Call->ReturnRegister, Tmp, Expected);
785 MachineIRBuilder &MIRBuilder,
788 return buildOpFromWrapper(MIRBuilder, Opcode, Call,
791 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
798 MIRBuilder, GR, MRI);
806 Semantics, MIRBuilder, GR);
822 MIRBuilder.getMF());
823 MIRBuilder.buildInstr(TargetOpcode::G_FNEG)
826 insertAssignInstr(NegValueReg, nullptr, Call->ReturnType, GR, MIRBuilder,
827 MIRBuilder.getMF().getRegInfo());
831 MIRBuilder.buildInstr(Opcode)
844 MachineIRBuilder &MIRBuilder,
849 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
863 MIRBuilder.buildInstr(Opcode)
876 unsigned Opcode, MachineIRBuilder &MIRBuilder,
881 return buildOpFromWrapper(MIRBuilder, Opcode, Call,
884 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
890 Semantics, MIRBuilder, GR);
900 buildScopeReg(ScopeRegister, SPIRV::Scope::Device, MIRBuilder, GR, MRI);
902 auto MIB = MIRBuilder.buildInstr(Opcode);
913 MachineIRBuilder &MIRBuilder,
916 return buildOpFromWrapper(MIRBuilder, Opcode, Call, Register(0));
918 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
944 MemSemanticsReg = buildConstantIntReg(MemSemantics, MIRBuilder, GR);
970 ScopeReg = buildConstantIntReg(Scope, MIRBuilder, GR);
972 auto MIB = MIRBuilder.buildInstr(Opcode).addUse(ScopeReg);
974 MIB.addUse(buildConstantIntReg(MemScope, MIRBuilder, GR));
1009 MachineIRBuilder &MIRBuilder,
1018 MIRBuilder.buildInstr(SPIRV::OpExtInst)
1030 MachineIRBuilder &MIRBuilder,
1040 buildBoolRegister(MIRBuilder, Call->ReturnType, GR);
1043 auto MIB = MIRBuilder.buildInstr(Opcode)
1051 return buildSelectInst(MIRBuilder, Call->ReturnRegister, CompareRegister,
1056 MachineIRBuilder &MIRBuilder,
1062 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
1065 return buildOpFromWrapper(MIRBuilder, GroupBuiltin->Opcode, Call,
1078 auto MIB = MIRBuilder.buildInstr(GroupBuiltin->Opcode)
1102 Arg0 = GR->buildConstantInt(getIConstVal(ConstRegister, MRI), MIRBuilder,
1103 GR->getOrCreateSPIRVBoolType(MIRBuilder));
1118 buildBoolRegister(MIRBuilder, Call->ReturnType, GR);
1122 Register ScopeRegister = buildConstantIntReg(Scope, MIRBuilder, GR);
1125 auto MIB = MIRBuilder.buildInstr(GroupBuiltin->Opcode)
1143 buildSelectInst(MIRBuilder, Call->ReturnRegister, GroupResultRegister,
1149 MachineIRBuilder &MIRBuilder,
1152 MachineFunction &MF = MIRBuilder.getMF();
1167 return buildOpFromWrapper(MIRBuilder, OpCode, Call,
1172 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
1205 ? MIRBuilder.buildInstr(OpCode)
1206 : MIRBuilder.buildInstr(OpCode)
1218 MachineIRBuilder &MIRBuilder,
1221 MachineFunction &MF = MIRBuilder.getMF();
1232 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
1258 auto MIB = MIRBuilder.buildInstr(GroupUniform->Opcode)
1269 MachineIRBuilder &MIRBuilder,
1272 MachineFunction &MF = MIRBuilder.getMF();
1281 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
1291 Register ScopeReg = buildConstantIntReg(ScopeArg, MIRBuilder, GR);
1293 MIRBuilder.buildInstr(SPIRV::OpReadClockKHR)
1328 MachineIRBuilder &MIRBuilder,
1336 GR->getOrCreateSPIRVIntegerType(PointerSize, MIRBuilder);
1337 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
1355 MIRBuilder.getMF());
1359 GR->buildConstantInt(DefaultValue, MIRBuilder, PointerSizeType);
1360 MIRBuilder.buildCopy(DefaultReg, NewRegister);
1363 GR->getOrCreateSPIRVVectorType(PointerSizeType, 3, MIRBuilder);
1365 buildBuiltinVariableLoad(MIRBuilder, Vec3Ty, GR, BuiltinValue,
1372 GR->assignSPIRVTypeToVReg(PointerSizeType, Extracted, MIRBuilder.getMF());
1376 MachineInstrBuilder ExtractInst = MIRBuilder.buildIntrinsic(
1382 insertAssignInstr(Extracted, nullptr, PointerSizeType, GR, MIRBuilder,
1386 auto BoolType = GR->getOrCreateSPIRVBoolType(MIRBuilder);
1391 GR->assignSPIRVTypeToVReg(BoolType, CompareRegister, MIRBuilder.getMF());
1394 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CompareRegister, IndexRegister,
1395 GR->buildConstantInt(3, MIRBuilder, IndexType));
1400 GR->buildConstantInt(DefaultValue, MIRBuilder, PointerSizeType);
1409 MIRBuilder.getMF());
1412 MIRBuilder.buildSelect(SelectionResult, CompareRegister, Extracted,
1421 MIRBuilder.buildZExtOrTrunc(Call->ReturnRegister, ToTruncate);
1426 MachineIRBuilder &MIRBuilder,
1434 return genWorkgroupQuery(Call, MIRBuilder, GR, Value, 0);
1445 return buildBuiltinVariableLoad(MIRBuilder, Call->ReturnType, GR, Value,
1450 MachineIRBuilder &MIRBuilder,
1459 return buildAtomicInitInst(Call, MIRBuilder);
1461 return buildAtomicLoadInst(Call, MIRBuilder, GR);
1463 return buildAtomicStoreInst(Call, MIRBuilder, GR);
1466 return buildAtomicCompareExchangeInst(Call, Builtin, Opcode, MIRBuilder,
1474 return buildAtomicRMWInst(Call, Opcode, MIRBuilder, GR);
1476 return buildBarrierInst(Call, SPIRV::OpMemoryBarrier, MIRBuilder, GR);
1479 return buildAtomicFlagInst(Call, Opcode, MIRBuilder, GR);
1482 return buildOpFromWrapper(MIRBuilder, Opcode, Call,
1489 MachineIRBuilder &MIRBuilder,
1499 return buildAtomicFloatingRMWInst(Call, Opcode, MIRBuilder, GR);
1506 MachineIRBuilder &MIRBuilder,
1513 return buildBarrierInst(Call, Opcode, MIRBuilder, GR);
1517 MachineIRBuilder &MIRBuilder) {
1518 MIRBuilder.buildInstr(TargetOpcode::G_ADDRSPACE_CAST)
1525 MachineIRBuilder &MIRBuilder,
1528 return buildOpFromWrapper(MIRBuilder, SPIRV::OpDot, Call,
1533 MIRBuilder.buildInstr(IsVec ? SPIRV::OpDot : SPIRV::OpFMulS)
1542 MachineIRBuilder &MIRBuilder,
1553 MIRBuilder, Call->ReturnType, GR, Value, LLType, Call->ReturnRegister,
1558 MachineIRBuilder &MIRBuilder,
1566 return genWorkgroupQuery(Call, MIRBuilder, GR, Value, IsDefault ? 1 : 0);
1570 MachineIRBuilder &MIRBuilder,
1589 QueryResult = MIRBuilder.getMRI()->createGenericVirtualRegister(
1591 MIRBuilder.getMRI()->setRegClass(QueryResult, &SPIRV::IDRegClass);
1592 SPIRVType *IntTy = GR->getOrCreateSPIRVIntegerType(32, MIRBuilder);
1594 IntTy, NumActualRetComponents, MIRBuilder);
1595 GR->assignSPIRVTypeToVReg(QueryResultType, QueryResult, MIRBuilder.getMF());
1600 MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
1601 auto MIB = MIRBuilder.buildInstr(Opcode)
1606 MIB.addUse(buildConstantIntReg(0, MIRBuilder, GR)); // Lod id.
1623 MIRBuilder.buildInstr(SPIRV::OpCompositeExtract)
1629 insertAssignInstr(Call->ReturnRegister, nullptr, NewType, GR, MIRBuilder,
1630 MIRBuilder.getMF().getRegInfo());
1633 auto MIB = MIRBuilder.buildInstr(SPIRV::OpVectorShuffle)
1645 MachineIRBuilder &MIRBuilder,
1656 MIRBuilder.getMRI()->setRegClass(Image, &SPIRV::IDRegClass);
1675 MIRBuilder.buildInstr(Opcode)
1716 MachineIRBuilder &MIRBuilder,
1719 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
1735 getSamplerFilterModeFromBitmask(SamplerMask), MIRBuilder,
1740 GR->getOrCreateOpTypeSampledImage(ImageType, MIRBuilder);
1743 MIRBuilder.buildInstr(SPIRV::OpSampledImage)
1750 MIRBuilder);
1755 GR->getOrCreateSPIRVVectorType(Call->ReturnType, 4, MIRBuilder);
1761 GR->assignSPIRVTypeToVReg(TempType, TempRegister, MIRBuilder.getMF());
1763 MIRBuilder.buildInstr(SPIRV::OpImageSampleExplicitLod)
1772 MIRBuilder.buildInstr(SPIRV::OpCompositeExtract)
1778 MIRBuilder.buildInstr(SPIRV::OpImageRead)
1786 MIRBuilder.buildInstr(SPIRV::OpImageRead)
1796 MachineIRBuilder &MIRBuilder,
1798 MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
1799 MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
1800 MIRBuilder.getMRI()->setRegClass(Call->Arguments[2], &SPIRV::IDRegClass);
1801 MIRBuilder.buildInstr(SPIRV::OpImageWrite)
1810 MachineIRBuilder &MIRBuilder,
1812 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
1820 getSamplerFilterModeFromBitmask(Bitmask), MIRBuilder, Call->ReturnType);
1827 GR->getOrCreateOpTypeSampledImage(ImageType, MIRBuilder);
1832 MIRBuilder.buildInstr(SPIRV::OpSampledImage)
1849 : GR->getOrCreateSPIRVTypeByName(ReturnType, MIRBuilder);
1859 MIRBuilder.buildInstr(SPIRV::OpImageSampleExplicitLod)
1872 MachineIRBuilder &MIRBuilder) {
1873 MIRBuilder.buildSelect(Call->ReturnRegister, Call->Arguments[0],
1879 MachineIRBuilder &MIRBuilder,
1881 return buildOpFromWrapper(MIRBuilder, SPIRV::OpCompositeConstruct, Call,
1886 MachineIRBuilder &MIRBuilder,
1899 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
1907 MIRBuilder.buildInstr(Opcode)
1913 return buildOpFromWrapper(MIRBuilder, Opcode, Call,
1918 MachineIRBuilder &MIRBuilder,
1924 const MachineRegisterInfo *MRI = MIRBuilder.getMRI();
1931 buildOpDecorate(Call->ReturnRegister, MIRBuilder, SPIRV::Decoration::SpecId,
1948 auto MIB = MIRBuilder.buildInstr(Opcode)
1961 auto MIB = MIRBuilder.buildInstr(Opcode)
1974 MachineIRBuilder &MIRBuilder,
1976 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
1983 MachineFunction &MF = MIRBuilder.getMF();
2014 SPIRVType *SpvFieldTy = GR->getOrCreateSPIRVType(FieldTy, MIRBuilder);
2017 MIRBuilder.buildInstr(SPIRV::OpLoad)
2022 cast<SPIRVSubtarget>(MIRBuilder.getMF().getSubtarget());
2023 Const = GR->getOrCreateConstIntArray(0, Size, *MIRBuilder.getInsertPt(),
2026 Const = GR->buildConstantInt(0, MIRBuilder, SpvTy);
2034 MIRBuilder.buildInstr(SPIRV::OpBuildNDRange)
2040 return MIRBuilder.buildInstr(SPIRV::OpStore)
2047 getOrCreateSPIRVDeviceEventPointer(MachineIRBuilder &MIRBuilder,
2049 LLVMContext &Context = MIRBuilder.getMF().getFunction().getContext();
2058 return GR->getOrCreateSPIRVType(PtrType, MIRBuilder);
2062 MachineIRBuilder &MIRBuilder,
2064 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
2065 const DataLayout &DL = MIRBuilder.getDataLayout();
2068 const SPIRVType *Int32Ty = GR->getOrCreateSPIRVIntegerType(32, MIRBuilder);
2089 Int32Ty, MIRBuilder, SPIRV::StorageClass::Function);
2093 GR->assignSPIRVTypeToVReg(PointerSizeTy, Reg, MIRBuilder.getMF());
2094 auto GEPInst = MIRBuilder.buildIntrinsic(
2099 .addUse(buildConstantIntReg(0, MIRBuilder, GR)) // Indices.
2100 .addUse(buildConstantIntReg(I, MIRBuilder, GR));
2106 auto MIB = MIRBuilder.buildInstr(SPIRV::OpEnqueueKernel)
2117 MIB.addUse(buildConstantIntReg(0, MIRBuilder, GR)); // Dummy num events.
2119 MIRBuilder, getOrCreateSPIRVDeviceEventPointer(MIRBuilder, GR));
2136 MIB.addUse(buildConstantIntReg(DL.getTypeStoreSize(PType), MIRBuilder, GR));
2139 buildConstantIntReg(DL.getPrefTypeAlign(PType).value(), MIRBuilder, GR));
2147 MachineIRBuilder &MIRBuilder,
2157 MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
2158 return MIRBuilder.buildInstr(Opcode).addUse(Call->Arguments[0]);
2161 return MIRBuilder.buildInstr(Opcode)
2165 MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
2166 return MIRBuilder.buildInstr(Opcode)
2171 MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
2172 MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
2173 return MIRBuilder.buildInstr(Opcode)
2177 MIRBuilder.getMRI()->setRegClass(Call->Arguments[0], &SPIRV::IDRegClass);
2178 MIRBuilder.getMRI()->setRegClass(Call->Arguments[1], &SPIRV::IDRegClass);
2179 MIRBuilder.getMRI()->setRegClass(Call->Arguments[2], &SPIRV::IDRegClass);
2180 return MIRBuilder.buildInstr(Opcode)
2185 return buildNDRange(Call, MIRBuilder, GR);
2187 return buildEnqueueKernel(Call, MIRBuilder, GR);
2194 MachineIRBuilder &MIRBuilder,
2204 return buildOpFromWrapper(MIRBuilder, Opcode, Call,
2207 auto Scope = buildConstantIntReg(SPIRV::Scope::Workgroup, MIRBuilder, GR);
2214 : GR->getOrCreateSPIRVTypeByName("spirv.Event", MIRBuilder);
2218 bool Res = MIRBuilder.buildInstr(Opcode)
2227 : buildConstantIntReg(1, MIRBuilder, GR))
2230 insertAssignInstr(Call->ReturnRegister, nullptr, NewType, GR, MIRBuilder,
2231 MIRBuilder.getMF().getRegInfo());
2235 return MIRBuilder.buildInstr(Opcode)
2246 MachineIRBuilder &MIRBuilder,
2256 return buildOpFromWrapper(MIRBuilder, Opcode, Call,
2261 buildOpDecorate(Call->ReturnRegister, MIRBuilder,
2264 buildOpDecorate(Call->ReturnRegister, MIRBuilder,
2286 &MIRBuilder.getMF().getSubtarget());
2307 &MIRBuilder.getMF().getSubtarget());
2342 MIRBuilder.buildInstr(Opcode)
2350 MachineIRBuilder &MIRBuilder,
2358 MIRBuilder.buildInstr(SPIRV::OpExtInst)
2376 MachineIRBuilder &MIRBuilder,
2384 auto MIB = MIRBuilder.buildInstr(Opcode);
2391 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
2487 MachineIRBuilder &MIRBuilder,
2497 ReturnType = GR->assignTypeToVReg(OrigRetTy, OrigRet, MIRBuilder);
2498 if (!MIRBuilder.getMRI()->getRegClassOrNull(ReturnRegister))
2499 MIRBuilder.getMRI()->setRegClass(ReturnRegister, &SPIRV::IDRegClass);
2501 ReturnRegister = MIRBuilder.getMRI()->createVirtualRegister(&IDRegClass);
2502 MIRBuilder.getMRI()->setType(ReturnRegister, LLT::scalar(32));
2503 ReturnType = GR->assignTypeToVReg(OrigRetTy, ReturnRegister, MIRBuilder);
2524 return generateExtInst(Call.get(), MIRBuilder, GR);
2526 return generateRelationalInst(Call.get(), MIRBuilder, GR);
2528 return generateGroupInst(Call.get(), MIRBuilder, GR);
2530 return generateBuiltinVar(Call.get(), MIRBuilder, GR);
2532 return generateAtomicInst(Call.get(), MIRBuilder, GR);
2534 return generateAtomicFloatingInst(Call.get(), MIRBuilder, GR);
2536 return generateBarrierInst(Call.get(), MIRBuilder, GR);
2538 return generateCastToPtrInst(Call.get(), MIRBuilder);
2540 return generateDotOrFMulInst(Call.get(), MIRBuilder, GR);
2542 return generateWaveInst(Call.get(), MIRBuilder, GR);
2544 return generateGetQueryInst(Call.get(), MIRBuilder, GR);
2546 return generateImageSizeQueryInst(Call.get(), MIRBuilder, GR);
2548 return generateImageMiscQueryInst(Call.get(), MIRBuilder, GR);
2550 return generateReadImageInst(DemangledCall, Call.get(), MIRBuilder, GR);
2552 return generateWriteImageInst(Call.get(), MIRBuilder, GR);
2554 return generateSampleImageInst(DemangledCall, Call.get(), MIRBuilder, GR);
2556 return generateSelectInst(Call.get(), MIRBuilder);
2558 return generateConstructInst(Call.get(), MIRBuilder, GR);
2560 return generateSpecConstantInst(Call.get(), MIRBuilder, GR);
2562 return generateEnqueueInst(Call.get(), MIRBuilder, GR);
2564 return generateAsyncCopy(Call.get(), MIRBuilder, GR);
2566 return generateConvertInst(DemangledCall, Call.get(), MIRBuilder, GR);
2568 return generateVectorLoadStoreInst(Call.get(), MIRBuilder, GR);
2570 return generateLoadStoreInst(Call.get(), MIRBuilder, GR);
2572 return generateIntelSubgroupsInst(Call.get(), MIRBuilder, GR);
2574 return generateGroupUniformInst(Call.get(), MIRBuilder, GR);
2576 return generateKernelClockInst(Call.get(), MIRBuilder, GR);
2578 return generateCoopMatrInst(Call.get(), MIRBuilder, GR);
2677 MachineIRBuilder &MIRBuilder,
2681 return GR->getOrCreateOpTypeByOpcode(ExtensionType, MIRBuilder, Opcode);
2684 static SPIRVType *getSamplerType(MachineIRBuilder &MIRBuilder,
2687 return GR->getOrCreateOpTypeSampler(MIRBuilder);
2691 MachineIRBuilder &MIRBuilder,
2696 return GR->getOrCreateOpTypePipe(MIRBuilder,
2702 MachineIRBuilder &MIRBuilder,
2709 GR->getOrCreateSPIRVType(ExtensionType->getTypeParameter(0), MIRBuilder);
2712 MIRBuilder, ExtensionType, ElemType, ExtensionType->getIntParameter(0),
2720 MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR) {
2724 GR->getOrCreateSPIRVType(ExtensionType->getTypeParameter(0), MIRBuilder);
2729 MIRBuilder, SampledType,
2741 MachineIRBuilder &MIRBuilder,
2744 OpaqueType, SPIRV::AccessQualifier::ReadOnly, MIRBuilder, GR);
2746 return GR->getOrCreateOpTypeSampledImage(OpaqueImageType, MIRBuilder);
2801 MachineIRBuilder &MIRBuilder,
2814 OpaqueType->getStructName().str(), MIRBuilder.getContext());
2816 unsigned NumStartingVRegs = MIRBuilder.getMRI()->getNumVirtRegs();
2833 TargetType = getImageType(BuiltinType, AccessQual, MIRBuilder, GR);
2836 TargetType = getPipeType(BuiltinType, MIRBuilder, GR);
2839 TargetType = GR->getOrCreateOpTypeDeviceEvent(MIRBuilder);
2842 TargetType = getSamplerType(MIRBuilder, GR);
2845 TargetType = getSampledImageType(BuiltinType, MIRBuilder, GR);
2848 TargetType = getCoopMatrType(BuiltinType, MIRBuilder, GR);
2852 getNonParameterizedType(BuiltinType, TypeRecord, MIRBuilder, GR);
2858 if (NumStartingVRegs < MIRBuilder.getMRI()->getNumVirtRegs())
2859 buildOpName(GR->getSPIRVTypeID(TargetType), Name, MIRBuilder);