Lines Matching defs:ISD
827 return ISD::VPSD;
831 return ISD::DELETED_NODE;
849 if (!LT.second.isVector() && TLI->isOperationCustom(ISD::FCEIL, LT.second))
957 if (TLI->isOperationCustom(ISD::VP_FRINT, LT.second))
965 if (TLI->isOperationCustom(ISD::VP_FRINT, LT.second))
1044 int ISD = TLI->InstructionOpcodeToISD(Opcode);
1045 assert(ISD && "Invalid opcode");
1049 switch (ISD) {
1050 case ISD::SIGN_EXTEND:
1051 case ISD::ZERO_EXTEND: {
1066 (ISD == ISD::SIGN_EXTEND) ? SExtOp[PowDiff - 1] : ZExtOp[PowDiff - 1];
1069 case ISD::TRUNCATE:
1080 case ISD::FP_EXTEND:
1081 case ISD::FP_ROUND: {
1086 unsigned Op = (ISD == ISD::TRUNCATE) ? RISCV::VNSRL_WI
1087 : (ISD == ISD::FP_EXTEND) ? RISCV::VFWCVT_F_F_V
1091 MVT ElementMVT = (ISD == ISD::TRUNCATE)
1101 case ISD::FP_TO_SINT:
1102 case ISD::FP_TO_UINT:
1103 case ISD::SINT_TO_FP:
1104 case ISD::UINT_TO_FP:
1258 int ISD = TLI->InstructionOpcodeToISD(Opcode);
1259 assert(ISD && "Invalid opcode");
1261 if (ISD != ISD::ADD && ISD != ISD::OR && ISD != ISD::XOR && ISD != ISD::AND &&
1262 ISD != ISD::FADD)
1269 if (ISD == ISD::AND) {
1302 switch (ISD) {
1303 case ISD::ADD:
1307 case ISD::OR:
1311 case ISD::XOR:
1315 case ISD::AND:
1319 case ISD::FADD:
1713 case ISD::ADD:
1714 case ISD::SUB:
1717 case ISD::SHL:
1718 case ISD::SRL:
1719 case ISD::SRA:
1722 case ISD::AND:
1723 case ISD::OR:
1724 case ISD::XOR:
1727 case ISD::MUL:
1728 case ISD::MULHS:
1729 case ISD::MULHU:
1732 case ISD::SDIV:
1733 case ISD::UDIV:
1736 case ISD::SREM:
1737 case ISD::UREM:
1740 case ISD::FADD:
1741 case ISD::FSUB:
1745 case ISD::FMUL:
1749 case ISD::FDIV:
1752 case ISD::FNEG: