Lines Matching full:mx
11 /// c is true if mx has the worst case behavior compared to LMULs in MxList.
14 class SiFive7IsWorstCaseMX<string mx, list<string> MxList> {
16 bit c = !eq(mx, LLMUL);
19 /// c is true if mx and sew have the worst case behavior compared to LMULs in
22 class SiFive7IsWorstCaseMXSEW<string mx, int sew, list<string> MxList,
25 defvar SSEW = SmallestSEW<mx, isF>.r;
26 bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));
31 class SiFive7GetCyclesDefault<string mx> {
33 !eq(mx, "M1") : 2,
34 !eq(mx, "M2") : 4,
35 !eq(mx, "M4") : 8,
36 !eq(mx, "M8") : 16,
37 !eq(mx, "MF2") : 1,
38 !eq(mx, "MF4") : 1,
39 !eq(mx, "MF8") : 1
43 class SiFive7GetCyclesNarrowing<string mx> {
45 !eq(mx, "M1") : 4,
46 !eq(mx, "M2") : 8,
47 !eq(mx, "M4") : 16,
48 !eq(mx, "MF2") : 2,
49 !eq(mx, "MF4") : 1,
50 !eq(mx, "MF8") : 1
54 class SiFive7GetCyclesVMask<string mx> {
56 !eq(mx, "M1") : 1,
57 !eq(mx, "M2") : 1,
58 !eq(mx, "M4") : 1,
59 !eq(mx, "M8") : 2,
60 !eq(mx, "MF2") : 1,
61 !eq(mx, "MF4") : 1,
62 !eq(mx, "MF8") : 1
68 class SiFive7GetMaskLoadStoreCycles<string mx> {
70 !eq(mx, "M8") : 2,
77 class SiFive7GetCyclesSegmentedSeg2<string mx> {
79 !eq(mx, "M1") : 4,
80 !eq(mx, "M2") : 8,
81 !eq(mx, "M4") : 16,
82 !eq(mx, "M8") : 32,
83 !eq(mx, "MF2") : 2,
84 !eq(mx, "MF4") : 1,
85 !eq(mx, "MF8") : 1
91 class SiFive7GetCyclesSegmented<string mx, int sew, int nf> {
96 !eq(mx, "M1") : !div(VLEN, sew),
97 !eq(mx, "M2") : !div(!mul(VLEN, 2), sew),
98 !eq(mx, "M4") : !div(!mul(VLEN, 4), sew),
99 !eq(mx, "M8") : !div(!mul(VLEN, 8), sew),
100 !eq(mx, "MF2") : !div(!div(VLEN, 2), sew),
101 !eq(mx, "MF4") : !div(!div(VLEN, 4), sew),
102 !eq(mx, "MF8") : !div(!div(VLEN, 8), sew),
110 class SiFive7GetCyclesOnePerElement<string mx, int sew> {
120 !eq(mx, "M1") : VLEN,
121 !eq(mx, "M2") : !mul(VLEN, 2),
122 !eq(mx, "M4") : !mul(VLEN, 4),
123 !eq(mx, "M8") : !mul(VLEN, 8),
124 !eq(mx, "MF2") : !div(VLEN, 2),
125 !eq(mx, "MF4") : !div(VLEN, 4),
126 !eq(mx, "MF8") : !div(VLEN, 8)
142 class SiFive7GetReductionCycles<string mx, int sew> {
148 !eq(mx, "M1") : 2,
149 !eq(mx, "M2") : 4,
150 !eq(mx, "M4") : 8,
151 !eq(mx, "M8") : 16,
152 !eq(mx, "MF2") : 1,
153 !eq(mx, "MF4") : 1,
154 !eq(mx, "MF8") : 1
163 class SiFive7GetOrderedReductionCycles<string mx, int sew> {
167 !eq(mx, "M1") : !div(VLEN, sew),
168 !eq(mx, "M2") : !div(!mul(VLEN, 2), sew),
169 !eq(mx, "M4") : !div(!mul(VLEN, 4), sew),
170 !eq(mx, "M8") : !div(!mul(VLEN, 8), sew),
171 !eq(mx, "MF2") : !div(!div(VLEN, 2), sew),
172 !eq(mx, "MF4") : !div(!div(VLEN, 4), sew),
173 !eq(mx, "MF8") : !div(!div(VLEN, 8), sew),
454 foreach mx = SchedMxList in {
455 defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
456 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
458 defm "" : LMULWriteResMX<"WriteVLDE", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>;
459 defm "" : LMULWriteResMX<"WriteVLDFF", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>;
462 defm "" : LMULWriteResMX<"WriteVSTE", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>;
465 foreach mx = SchedMxList in {
466 defvar Cycles = SiFive7GetMaskLoadStoreCycles<mx>.c;
467 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
469 defm "" : LMULWriteResMX<"WriteVLDM", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>;
471 defm "" : LMULWriteResMX<"WriteVSTM", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>;
486 foreach mx = SchedMxList in {
487 defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
488 defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 8>.c;
489 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
492 [0, 1], [1, !add(1, Cycles)], mx, IsWorstCase>;
494 defm "" : LMULWriteResMX<"WriteVLDUX8", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>;
495 defm "" : LMULWriteResMX<"WriteVLDOX8", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>;
498 defm "" : LMULWriteResMX<"WriteVSTS8", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>;
499 defm "" : LMULWriteResMX<"WriteVSTUX8", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>;
500 defm "" : LMULWriteResMX<"WriteVSTOX8", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>;
506 foreach mx = ["MF4", "MF2", "M1", "M2", "M4", "M8"] in {
507 defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
508 defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 16>.c;
509 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
512 [0, 1], [1, !add(1, Cycles)], mx, IsWorstCase>;
514 defm "" : LMULWriteResMX<"WriteVLDUX16", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>;
515 defm "" : LMULWriteResMX<"WriteVLDOX16", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>;
518 defm "" : LMULWriteResMX<"WriteVSTS16", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>;
519 defm "" : LMULWriteResMX<"WriteVSTUX16", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>;
520 defm "" : LMULWriteResMX<"WriteVSTOX16", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>;
523 foreach mx = ["MF2", "M1", "M2", "M4", "M8"] in {
524 defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
525 defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 32>.c;
526 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
529 [0, 1], [1, !add(1, Cycles)], mx, IsWorstCase>;
531 defm "" : LMULWriteResMX<"WriteVLDUX32", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>;
532 defm "" : LMULWriteResMX<"WriteVLDOX32", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>;
535 defm "" : LMULWriteResMX<"WriteVSTS32", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>;
536 defm "" : LMULWriteResMX<"WriteVSTUX32", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>;
537 defm "" : LMULWriteResMX<"WriteVSTOX32", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>;
540 foreach mx = ["M1", "M2", "M4", "M8"] in {
541 defvar VLDSX0Cycles = SiFive7GetCyclesDefault<mx>.c;
542 defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 64>.c;
543 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
546 [0, 1], [1, !add(1, Cycles)], mx, IsWorstCase>;
548 defm "" : LMULWriteResMX<"WriteVLDUX64", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>;
549 defm "" : LMULWriteResMX<"WriteVLDOX64", [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>;
552 defm "" : LMULWriteResMX<"WriteVSTS64", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>;
553 defm "" : LMULWriteResMX<"WriteVSTUX64", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>;
554 defm "" : LMULWriteResMX<"WriteVSTOX64", [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>;
583 foreach mx = SchedMxList in {
585 defvar Cycles = SiFive7GetCyclesSegmentedSeg2<mx>.c;
586 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
589 defm "" : LMULWriteResMX<"WriteVLSEG2e" # eew, [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>;
590 defm "" : LMULWriteResMX<"WriteVLSEGFF2e" # eew, [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>;
593 defm "" : LMULWriteResMX<"WriteVSSEG2e" # eew, [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>;
595 defvar Cycles = SiFive7GetCyclesSegmented<mx, eew, nf>.c;
596 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
599 defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" # eew, [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>;
600 defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" # eew, [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>;
603 defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" # eew, [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>;
607 foreach mx = SchedMxList in {
610 defvar Cycles = SiFive7GetCyclesSegmented<mx, eew, nf>.c;
611 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
614 defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" # eew, [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>;
615 defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" # eew, [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>;
616 defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" # eew, [SiFive7VCQ, SiFive7VL], mx, IsWorstCase>;
619 defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" # eew, [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>;
620 defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" # eew, [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>;
621 defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" # eew, [SiFive7VCQ, SiFive7VS], mx, IsWorstCase>;
628 foreach mx = SchedMxList in {
629 defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
630 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
632 defm "" : LMULWriteResMX<"WriteVIALUV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
633 defm "" : LMULWriteResMX<"WriteVIALUX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
634 defm "" : LMULWriteResMX<"WriteVIALUI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
635 defm "" : LMULWriteResMX<"WriteVICALUV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
636 defm "" : LMULWriteResMX<"WriteVICALUX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
637 defm "" : LMULWriteResMX<"WriteVICALUI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
638 defm "" : LMULWriteResMX<"WriteVShiftV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
639 defm "" : LMULWriteResMX<"WriteVShiftX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
640 defm "" : LMULWriteResMX<"WriteVShiftI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
641 defm "" : LMULWriteResMX<"WriteVIMinMaxV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
642 defm "" : LMULWriteResMX<"WriteVIMinMaxX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
643 defm "" : LMULWriteResMX<"WriteVIMulV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
644 defm "" : LMULWriteResMX<"WriteVIMulX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
645 defm "" : LMULWriteResMX<"WriteVIMulAddV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
646 defm "" : LMULWriteResMX<"WriteVIMulAddX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
647 defm "" : LMULWriteResMX<"WriteVIMergeV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
648 defm "" : LMULWriteResMX<"WriteVIMergeX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
649 defm "" : LMULWriteResMX<"WriteVIMergeI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
650 defm "" : LMULWriteResMX<"WriteVIMovV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
651 defm "" : LMULWriteResMX<"WriteVIMovX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
652 defm "" : LMULWriteResMX<"WriteVIMovI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
656 defm "" : LMULWriteResMX<"WriteVICmpV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
657 defm "" : LMULWriteResMX<"WriteVICmpX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
658 defm "" : LMULWriteResMX<"WriteVICmpI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
661 foreach mx = SchedMxList in {
662 defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
663 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
665 defm "" : LMULWriteResMX<"WriteVExtV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
668 foreach mx = SchedMxList in {
669 foreach sew = SchedSEWSet<mx>.val in {
671 !div(SiFive7GetCyclesOnePerElement<mx, sew>.c, 4));
672 defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
674 defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
675 defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
681 foreach mx = SchedMxListW in {
682 defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
683 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
685 defm "" : LMULWriteResMX<"WriteVIWALUV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
686 defm "" : LMULWriteResMX<"WriteVIWALUX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
687 defm "" : LMULWriteResMX<"WriteVIWALUI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
688 defm "" : LMULWriteResMX<"WriteVIWMulV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
689 defm "" : LMULWriteResMX<"WriteVIWMulX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
690 defm "" : LMULWriteResMX<"WriteVIWMulAddV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
691 defm "" : LMULWriteResMX<"WriteVIWMulAddX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
695 foreach mx = SchedMxListW in {
696 defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
697 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
699 defm "" : LMULWriteResMX<"WriteVNShiftV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
700 defm "" : LMULWriteResMX<"WriteVNShiftX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
701 defm "" : LMULWriteResMX<"WriteVNShiftI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
706 foreach mx = SchedMxList in {
707 defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
708 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
710 defm "" : LMULWriteResMX<"WriteVSALUV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
711 defm "" : LMULWriteResMX<"WriteVSALUX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
712 defm "" : LMULWriteResMX<"WriteVSALUI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
713 defm "" : LMULWriteResMX<"WriteVAALUV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
714 defm "" : LMULWriteResMX<"WriteVAALUX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
715 defm "" : LMULWriteResMX<"WriteVSMulV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
716 defm "" : LMULWriteResMX<"WriteVSMulX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
717 defm "" : LMULWriteResMX<"WriteVSShiftV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
718 defm "" : LMULWriteResMX<"WriteVSShiftX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
719 defm "" : LMULWriteResMX<"WriteVSShiftI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
723 foreach mx = SchedMxListW in {
724 defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
725 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
727 defm "" : LMULWriteResMX<"WriteVNClipV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
728 defm "" : LMULWriteResMX<"WriteVNClipX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
729 defm "" : LMULWriteResMX<"WriteVNClipI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
734 foreach mx = SchedMxListF in {
735 foreach sew = SchedSEWSet<mx, isF=1>.val in {
736 defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
737 defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
739 defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
740 defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
741 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
742 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
743 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
744 defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
745 defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
746 defm "" : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
749 defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
750 defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxF", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
751 defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
752 defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjF", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
756 foreach mx = SchedMxList in {
757 defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
758 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
760 defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
763 defm "" : LMULWriteResMX<"WriteVFClassV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
764 defm "" : LMULWriteResMX<"WriteVFMergeV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
765 defm "" : LMULWriteResMX<"WriteVFMovV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
769 defm "" : LMULWriteResMX<"WriteVFCmpV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
770 defm "" : LMULWriteResMX<"WriteVFCmpF", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
773 foreach mx = SchedMxListF in {
774 foreach sew = SchedSEWSet<mx, isF=1>.val in {
776 !div(SiFive7GetCyclesOnePerElement<mx, sew>.c, 4));
777 defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
779 defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
780 defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
781 defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
787 foreach mx = SchedMxListW in {
788 foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {
789 defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
790 defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;
792 defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
795 foreach mx = SchedMxListFW in {
796 foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
797 defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
798 defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
800 defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
801 defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUF", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
802 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
803 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulF", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
804 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
805 defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddF", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
806 defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtFToFV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
809 defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
810 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListFW>.c;
812 defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
815 foreach mx = SchedMxListW in {
816 defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
817 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
819 defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
822 foreach mx = SchedMxListFW in {
823 foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
824 defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
825 defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
827 defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
828 defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
834 foreach mx = SchedMxList in {
835 foreach sew = SchedSEWSet<mx>.val in {
836 defvar Cycles = SiFive7GetReductionCycles<mx, sew>.c;
837 defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
840 mx, sew, IsWorstCase>;
842 mx, sew, IsWorstCase>;
847 foreach mx = SchedMxListWRed in {
848 foreach sew = SchedSEWSet<mx, 0, 1>.val in {
849 defvar Cycles = SiFive7GetReductionCycles<mx, sew>.c;
850 defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;
853 mx, sew, IsWorstCase>;
857 foreach mx = SchedMxListF in {
858 foreach sew = SchedSEWSet<mx, 1>.val in {
859 defvar RedCycles = SiFive7GetReductionCycles<mx, sew>.c;
860 defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
863 mx, sew, IsWorstCase>;
865 mx, sew, IsWorstCase>;
867 defvar OrdRedCycles = SiFive7GetOrderedReductionCycles<mx, sew>.c;
870 mx, sew, IsWorstCase>;
874 foreach mx = SchedMxListFWRed in {
875 foreach sew = SchedSEWSet<mx, 1, 1>.val in {
876 defvar RedCycles = SiFive7GetReductionCycles<mx, sew>.c;
877 defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListFWRed, 1>.c;
880 mx, sew, IsWorstCase>;
881 defvar OrdRedCycles = SiFive7GetOrderedReductionCycles<mx, sew>.c;
884 mx, sew, IsWorstCase>;
889 foreach mx = SchedMxList in {
890 defvar Cycles = SiFive7GetCyclesVMask<mx>.c;
891 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
893 defm "" : LMULWriteResMX<"WriteVMALUV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
894 defm "" : LMULWriteResMX<"WriteVMPopV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
895 defm "" : LMULWriteResMX<"WriteVMFFSV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
896 defm "" : LMULWriteResMX<"WriteVMSFSV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
899 foreach mx = SchedMxList in {
900 defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
901 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
903 defm "" : LMULWriteResMX<"WriteVIotaV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
904 defm "" : LMULWriteResMX<"WriteVIdxV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
915 foreach mx = SchedMxList in {
916 defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
917 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
919 defm "" : LMULWriteResMX<"WriteVRGatherVX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
920 defm "" : LMULWriteResMX<"WriteVRGatherVI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
924 foreach mx = SchedMxList in {
925 foreach sew = SchedSEWSet<mx>.val in {
926 defvar Cycles = SiFive7GetCyclesOnePerElement<mx, sew>.c;
927 defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
929 defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
930 defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherEI16VV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
931 defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
936 foreach mx = SchedMxList in {
937 defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
938 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
940 defm "" : LMULWriteResMX<"WriteVSlideUpX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
941 defm "" : LMULWriteResMX<"WriteVSlideDownX", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
942 defm "" : LMULWriteResMX<"WriteVSlideI", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
943 defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
944 defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
973 foreach mx = SchedMxList in {
974 defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
975 defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
979 defm "" : LMULWriteResMX<"WriteVC_V_I", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
980 defm "" : LMULWriteResMX<"WriteVC_V_X", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
981 defm "" : LMULWriteResMX<"WriteVC_V_IV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
982 defm "" : LMULWriteResMX<"WriteVC_V_VV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
983 defm "" : LMULWriteResMX<"WriteVC_V_XV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
984 defm "" : LMULWriteResMX<"WriteVC_V_IVV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
985 defm "" : LMULWriteResMX<"WriteVC_V_IVW", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
986 defm "" : LMULWriteResMX<"WriteVC_V_VVV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
987 defm "" : LMULWriteResMX<"WriteVC_V_VVW", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
988 defm "" : LMULWriteResMX<"WriteVC_V_XVV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
989 defm "" : LMULWriteResMX<"WriteVC_V_XVW", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
991 defm "" : LMULWriteResMX<"WriteVC_V_" # f # "V", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
992 defm "" : LMULWriteResMX<"WriteVC_V_" # f # "VV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
993 defm "" : LMULWriteResMX<"WriteVC_V_" # f # "VW", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
995 defm "" : LMULWriteResMX<"WriteVC_I", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
996 defm "" : LMULWriteResMX<"WriteVC_X", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
997 defm "" : LMULWriteResMX<"WriteVC_IV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
998 defm "" : LMULWriteResMX<"WriteVC_VV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
999 defm "" : LMULWriteResMX<"WriteVC_XV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
1000 defm "" : LMULWriteResMX<"WriteVC_IVV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
1001 defm "" : LMULWriteResMX<"WriteVC_IVW", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
1002 defm "" : LMULWriteResMX<"WriteVC_VVV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
1003 defm "" : LMULWriteResMX<"WriteVC_VVW", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
1004 defm "" : LMULWriteResMX<"WriteVC_XVV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
1005 defm "" : LMULWriteResMX<"WriteVC_XVW", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
1007 defm "" : LMULWriteResMX<"WriteVC_" # f # "V", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
1008 defm "" : LMULWriteResMX<"WriteVC_" # f # "VV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
1009 defm "" : LMULWriteResMX<"WriteVC_" # f # "VW", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
1291 foreach mx = SchedMxList in {
1292 def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx), 0>;
1293 foreach sew = SchedSEWSet<mx>.val in
1294 def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # sew), 0>;