Lines Matching +full:sw +full:- +full:exception
1 //===-- RISCVMakeCompressible.cpp - Make more instructions compressible ---===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
21 // sw zero, 0(a0) # if zero
22 // sw zero, 8(a0) # if zero
23 // sw zero, 4(a0) # if zero
24 // sw zero, 24(a0) # if zero
29 // c.sw a1, 0(a0)
30 // c.sw a1, 8(a0)
31 // c.sw a1, 4(a0)
32 // c.sw a1, 24(a0)
41 // For example, the following offsets are too large for c.sw:
43 // sw a1, -236(a2)
44 // sw a1, -240(a2)
45 // sw a1, -244(a2)
46 // sw a1, -248(a2)
47 // sw a1, -252(a2)
48 // sw a0, -256(a2)
54 // addi a3, a2, -256
55 // c.sw a1, 20(a3)
56 // c.sw a1, 16(a3)
57 // c.sw a1, 12(a3)
58 // c.sw a1, 8(a3)
59 // c.sw a1, 4(a3)
60 // c.sw a0, 0(a3)
66 //===----------------------------------------------------------------------===//
77 #define DEBUG_TYPE "riscv-make-compressible"
78 #define RISCV_COMPRESS_INSTRS_NAME "RISC-V Make Compressible"
94 INITIALIZE_PASS(RISCVMakeCompressibleOpt, "riscv-make-compressible",
110 case RISCV::SW:
135 case RISCV::SW:
146 // Return a mask for the offset bits of a non-stack-pointer based compressed
152 // Return true if Offset fits within a compressed stack-pointer based
155 // Compressed sp-based loads and stores only work for 32/64 bits.
182 const RISCVSubtarget &STI = MI.getMF()->getSubtarget<RISCVSubtarget>();
203 const RISCVSubtarget &STI = MI.getMF()->getSubtarget<RISCVSubtarget>();
211 case RISCV::SW:
226 // {Reg, 0} - Uncompressed Reg needs replacing with a compressed
228 // {Reg, N} - Reg needs replacing with a compressed register and
231 // {RISCV::NoRegister, 0} - No suitable optimization found for this
286 MBB.getParent()->getSubtarget().getRegisterInfo();
301 // possible to optimize a large offset in the current instruction - this
332 RS.backward(std::next(MIs.back()->getIterator()));