Lines Matching full:mx

256     def "_" # MInfo.MX : VPseudoBinaryNoMaskPolicy<RetClass, Op1Class, Op2Class,
266 def "_" # MInfo.MX : VPseudoTernaryNoMask_Zvk<RetClass, Op1Class, Op2Class>;
271 def "_VV_" # m.MX : VPseudoBinaryNoMask_Zvk<m.vrclass, m.vrclass>;
277 foreach vs2_lmul = ZvkMxSet<m.MX>.vs2_lmuls in
278 def "_VS_" # m.MX # "_" # vs2_lmul.MX : VPseudoBinaryNoMask_Zvk<m.vrclass, vs2_lmul.vrclass>;
283 defvar mx = m.MX;
285 SchedBinary<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV", mx>;
291 defvar mx = m.MX;
293 SchedBinary<"WriteVAESMVV", "ReadVAESMVV", "ReadVAESMVV", mx>;
295 SchedBinary<"WriteVAESMVV", "ReadVAESMVV", "ReadVAESMVV", mx>;
302 defvar mx = m.MX;
304 SchedBinary<"WriteVSM4RV", "ReadVSM4RV", "ReadVSM4RV", mx>;
306 SchedBinary<"WriteVSM4RV", "ReadVSM4RV", "ReadVSM4RV", mx>;
313 defvar mx = m.MX;
316 "ReadVGHSHV", mx>;
322 defvar mx = m.MX;
325 "ReadVSHA2CHV", mx>;
331 defvar mx = m.MX;
334 "ReadVSHA2CLV", mx>;
340 defvar mx = m.MX;
343 "ReadVSHA2MSV", mx>;
349 defvar mx = m.MX;
351 SchedBinary<"WriteVAESKF1V", "ReadVAESKF1V", "ReadVAESKF1V", mx,
358 defvar mx = m.MX;
361 "ReadVAESKF2V", mx>;
367 defvar mx = m.MX;
369 SchedBinary<"WriteVAESZV", "ReadVAESZV", "ReadVAESZV", mx>;
375 defvar mx = m.MX;
378 "ReadVSM3CV", mx>;
384 defvar mx = m.MX;
386 SchedBinary<"WriteVSM4KV", "ReadVSM4KV", "ReadVSM4KV", mx,
393 defvar mx = m.MX;
395 SchedBinary<"WriteVSM3MEV", "ReadVSM3MEV", "ReadVSM3MEV", mx,
402 defvar mx = m.MX;
404 SchedBinary<"WriteVCLMULV", "ReadVCLMULV", "ReadVCLMULV", mx,
407 SchedBinary<"WriteVCLMULX", "ReadVCLMULV", "ReadVCLMULX", mx,
414 defvar suffix = "_V_" # m.MX;
423 defvar mx = m.MX;
425 SchedUnary<"WriteVBREVV", "ReadVBREVV", mx, forceMergeOpRead=true>;
431 defvar mx = m.MX;
433 SchedUnary<"WriteVCLZV", "ReadVCLZV", mx, forceMergeOpRead=true>;
439 defvar mx = m.MX;
441 SchedUnary<"WriteVCTZV", "ReadVCTZV", mx, forceMergeOpRead=true>;
447 defvar mx = m.MX;
449 SchedUnary<"WriteVCPOPV", "ReadVCPOPV", mx, forceMergeOpRead=true>;
455 defvar mx = m.MX;
457 SchedBinary<"WriteVWSLLV", "ReadVWSLLV", "ReadVWSLLV", mx,
460 SchedBinary<"WriteVWSLLX", "ReadVWSLLV", "ReadVWSLLX", mx,
463 SchedUnary<"WriteVWSLLI", "ReadVWSLLV", mx,
471 SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", m.MX,
474 SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", m.MX,
481 defvar mx = m.MX;
483 SchedUnary<"WriteVBREV8V", "ReadVBREV8V", mx, forceMergeOpRead=true>;
489 defvar mx = m.MX;
491 SchedUnary<"WriteVREV8V", "ReadVREV8V", mx, forceMergeOpRead=true>;
498 SchedBinary<"WriteVRotV", "ReadVRotV", "ReadVRotV", m.MX,
501 SchedBinary<"WriteVRotX", "ReadVRotV", "ReadVRotX", m.MX,
510 SchedUnary<"WriteVRotI", "ReadVRotV", m.MX,
577 (!cast<Instruction>(instruction_name#"_V_"#vti.LMul.MX)
597 (!cast<Instruction>("PseudoVANDN_VV_"#vti.LMul.MX)
605 (!cast<Instruction>("PseudoVANDN_VX_"#vti.LMul.MX)
646 (!cast<Instruction>("PseudoVROR_VI_"#vti.LMul.MX)
663 (!cast<Instruction>("PseudoVWSLL_VV_"#vti.LMul.MX)
670 (!cast<Instruction>("PseudoVWSLL_VX_"#vti.LMul.MX)
677 (!cast<Instruction>("PseudoVWSLL_VI_"#vti.LMul.MX)
697 (!cast<Instruction>(instruction_name#"_V_"#vti.LMul.MX#"_MASK")
721 (!cast<Instruction>("PseudoVANDN_VV_"#vti.LMul.MX#"_MASK")
736 (!cast<Instruction>("PseudoVANDN_VX_"#vti.LMul.MX#"_MASK")
763 (!cast<Instruction>("PseudoVROR_VI_"#vti.LMul.MX#"_MASK")
783 (!cast<Instruction>("PseudoVWSLL_VV_"#vti.LMul.MX#"_MASK")
796 (!cast<Instruction>("PseudoVWSLL_VV_"#vti.LMul.MX#"_MASK")
805 (!cast<Instruction>("PseudoVWSLL_VX_"#vti.LMul.MX#"_MASK")
816 (!cast<Instruction>("PseudoVWSLL_VX_"#vti.LMul.MX#"_MASK")
825 (!cast<Instruction>("PseudoVWSLL_VI_"#vti.LMul.MX#"_MASK")
836 (!cast<Instruction>("PseudoVWSLL_VI_"#vti.LMul.MX#"_MASK")
845 (!cast<Instruction>("PseudoVWSLL_VV_"#vti.LMul.MX#"_MASK")
854 (!cast<Instruction>("PseudoVWSLL_VX_"#vti.LMul.MX#"_MASK")
863 (!cast<Instruction>("PseudoVWSLL_VI_"#vti.LMul.MX#"_MASK")
886 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
905 (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_"#vs2_lmul.MX)
921 foreach vti_vs2 = ZvkI32IntegerVectors<vti.LMul.MX>.vs2_types in
956 def : VPatBinaryNoMaskTU<intrinsic, instruction # "_VI_" # vti.LMul.MX,
964 def : VPatBinaryNoMaskTU<intrinsic, instruction # "_VV_" # vti.LMul.MX,
976 instruction#"_"#kind#"_"#vti.LMul.MX#"_E"#vti.SEW,
977 instruction#"_"#kind#"_"#vti.LMul.MX),
989 !if(isSEWAware, instruction#"_VI_"#vti.LMul.MX#"_E"#vti.SEW,
990 instruction#"_VI_"#vti.LMul.MX));
1003 !if(isSEWAware, instruction#"_VI_"#vti.LMul.MX#"_E"#vti.SEW#"_MASK",
1004 instruction#"_VI_"#vti.LMul.MX#"_MASK"));
1040 defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX,
1044 defm : VPatBinary<intrinsic, instruction # "_VI_" # Vti.LMul.MX,