Lines Matching +full:24 +full:- +full:bit

1 //===-- RISCVInstrFormatsV.td - RISC-V V Instruction Formats -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //  This file describes the RISC-V V extension instruction formats.
11 //===----------------------------------------------------------------------===//
65   let Inst{29-20} = vtypei{9-0};
66   let Inst{19-15} = uimm;
67   let Inst{14-12} = OPCFG.Value;
68   let Inst{11-7} = rd;
69   let Inst{6-0} = OPC_OP_V.Value;
81   let Inst{30-20} = vtypei;
82   let Inst{19-15} = rs1;
83   let Inst{14-12} = OPCFG.Value;
84   let Inst{11-7} = rd;
85   let Inst{6-0} = OPC_OP_V.Value;
97   let Inst{30-25} = 0b000000;
98   let Inst{24-20} = rs2;
99   let Inst{19-15} = rs1;
100   let Inst{14-12} = OPCFG.Value;
101   let Inst{11-7} = rd;
102   let Inst{6-0} = OPC_OP_V.Value;
113   bit vm;
115   let Inst{31-26} = funct6;
117   let Inst{24-20} = vs2;
118   let Inst{19-15} = vs1;
119   let Inst{14-12} = opv.Value;
120   let Inst{11-7} = vd;
121   let Inst{6-0} = OPC_OP_V.Value;
133   bit vm;
135   let Inst{31-26} = funct6;
137   let Inst{24-20} = vs2;
138   let Inst{19-15} = rs1;
139   let Inst{14-12} = opv.Value;
140   let Inst{11-7} = vd;
141   let Inst{6-0} = OPC_OP_V.Value;
152   bit vm;
154   let Inst{31-26} = funct6;
156   let Inst{24-20} = vs2;
157   let Inst{19-15} = rs1;
158   let Inst{14-12} = opv.Value;
159   let Inst{11-7} = vd;
160   let Inst{6-0} = OPC_OP_V.Value;
172   bit vm;
174   let Inst{31-26} = funct6;
176   let Inst{24-20} = vs2;
177   let Inst{19-15} = imm;
178   let Inst{14-12} = OPIVI.Value;
179   let Inst{11-7} = vd;
180   let Inst{6-0} = OPC_OP_V.Value;
191   bit vm;
193   let Inst{31-26} = funct6;
195   let Inst{24-20} = vs2;
196   let Inst{19-15} = vs1;
197   let Inst{14-12} = opv.Value;
198   let Inst{11-7} = vd;
199   let Inst{6-0} = OPC_OP_V.Value;
205 class RVInstVLU<bits<3> nf, bit mew, RISCVLSUMOP lumop,
211   bit vm;
213   let Inst{31-29} = nf;
215   let Inst{27-26} = MOPLDUnitStride.Value;
217   let Inst{24-20} = lumop.Value;
218   let Inst{19-15} = rs1;
219   let Inst{14-12} = width;
220   let Inst{11-7} = vd;
221   let Inst{6-0} = OPC_LOAD_FP.Value;
227 class RVInstVLS<bits<3> nf, bit mew, bits<3> width,
233   bit vm;
235   let Inst{31-29} = nf;
237   let Inst{27-26} = MOPLDStrided.Value;
239   let Inst{24-20} = rs2;
240   let Inst{19-15} = rs1;
241   let Inst{14-12} = width;
242   let Inst{11-7} = vd;
243   let Inst{6-0} = OPC_LOAD_FP.Value;
249 class RVInstVLX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
255   bit vm;
257   let Inst{31-29} = nf;
259   let Inst{27-26} = mop.Value;
261   let Inst{24-20} = vs2;
262   let Inst{19-15} = rs1;
263   let Inst{14-12} = width;
264   let Inst{11-7} = vd;
265   let Inst{6-0} = OPC_LOAD_FP.Value;
271 class RVInstVSU<bits<3> nf, bit mew, RISCVLSUMOP sumop,
277   bit vm;
279   let Inst{31-29} = nf;
281   let Inst{27-26} = MOPSTUnitStride.Value;
283   let Inst{24-20} = sumop.Value;
284   let Inst{19-15} = rs1;
285   let Inst{14-12} = width;
286   let Inst{11-7} = vs3;
287   let Inst{6-0} = OPC_STORE_FP.Value;
292 class RVInstVSS<bits<3> nf, bit mew, bits<3> width,
298   bit vm;
300   let Inst{31-29} = nf;
302   let Inst{27-26} = MOPSTStrided.Value;
304   let Inst{24-20} = rs2;
305   let Inst{19-15} = rs1;
306   let Inst{14-12} = width;
307   let Inst{11-7} = vs3;
308   let Inst{6-0} = OPC_STORE_FP.Value;
313 class RVInstVSX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
319   bit vm;
321   let Inst{31-29} = nf;
323   let Inst{27-26} = mop.Value;
325   let Inst{24-20} = vs2;
326   let Inst{19-15} = rs1;
327   let Inst{14-12} = width;
328   let Inst{11-7} = vs3;
329   let Inst{6-0} = OPC_STORE_FP.Value;