Lines Matching full:semantics

68   // RV64I shifts, directly matching the semantics of the named RISC-V
79   // RV64IB rotates, directly matching the semantics of the named RISC-V
83   // RV64IZbb bit counting instructions directly matching the semantics of the
94   // FMV_H_X matches the semantics of the FMV.H.X.
97   // FMV_W_X_RV64 matches the semantics of the FMV.W.X.
132   // Floating point fmax and fmin matching the RISC-V instruction semantics.
158   // VMV_V_V_VL matches the semantics of vmv.v.v but includes an extra operand
162   // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
166   // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
170   // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign
173   // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand.
175   // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand.
184   // Matches the semantics of vslideup/vslidedown. The first operand is the
190   // Matches the semantics of vslide1up/slide1down. The first operand is
195   // Matches the semantics of vfslide1up/vfslide1down. The first operand is
201   // Matches the semantics of the vid.v instruction, with a mask and VL
204   // Matches the semantics of the vfcnvt.rod function (Convert double-width
209   // These nodes match the semantics of the corresponding RVV vector reduction
370   // Matches the semantics of vrgather.vx and vrgather.vv with extra operands
406   // Branchless select operations, matching the semantics of the instructions