Lines Matching defs:SEW
2707 // each fractional LMUL we support SEW between 8 and LMUL*ELEN.
4809 // twice the SEW (Hence the restriction on not using the maximum
5135 // If this is SEW=64 on RV32, use a strided load with a stride of x0.
8077 // Custom-lower a SPLAT_VECTOR_PARTS where XLEN<SEW, as the SEW element type is
8244 // RVV only has truncates which operate from SEW*2->SEW, so lower arbitrary
8813 // that a widening operation never uses SEW=64.
8824 // instruction to sign-extend since SEW>XLEN.
8846 // Double the VL since we halved SEW.
8863 SDValue SEW = DAG.getConstant(Sew, DL, XLenVT);
8866 I32VL = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, XLenVT, SETVLMAX, SEW,
8878 SDValue SEW = DAG.getConstant(Sew, DL, XLenVT);
8884 SEW, LMUL);
8891 // Shift the two scalar parts in using SEW=32 slide1up/slide1down
8948 // SEW=8 for the vsetvli because it is the only element width that supports all
8949 // fractional LMULs. The LMUL is choosen so that with SEW=8 the VLMax is
8952 // SEW and LMUL are better for the surrounding vector instructions.
9071 // LMUL * VLEN should be greater than or equal to EGS * SEW
9290 report_fatal_error("EGW should be greater than or equal to 4 * SEW.");
9298 report_fatal_error("EGW should be greater than or equal to 8 * SEW.");
9301 // zvknha(SEW=32)/zvknhb(SEW=[32|64])
9307 report_fatal_error("SEW=64 needs Zvknhb to be enabled.");
9311 report_fatal_error("EGW should be greater than or equal to 4 * SEW.");
10502 // For the indices, use the same SEW to avoid an extra vsetvli
10646 // TODO: This code assumes VLMAX <= 65536 for LMUL=8 SEW=16.
10666 // If this is SEW=8 and VLMAX is potentially more than 256, we need
10698 // Calculate VLMAX-1 for the desired SEW.
10703 // Splat VLMAX-1 taking care to handle SEW==64 on RV32.
11689 // If this is SEW=8 and VLMAX is unknown or more than 256, we need
11693 // NOTE: This code assumes VLMAX <= 65536 for LMUL=8 SEW=16.
12660 // Custom-legalize an EXTRACT_VECTOR_ELT where XLEN<SEW, as the SEW element
12662 // With vmv.x.s, when SEW > XLEN, only the least-significant XLEN bits are
12664 // upper- and lower- halves of the SEW-bit vector element, slid down to the
16470 // n-levels TRUNCATE_VECTOR_VL to satisfy RVV's SEW*2->SEW truncate
17931 unsigned SEW = RISCVVType::decodeVSEW(VSEW);
17933 uint64_t MaxVL = Subtarget.getRealMaxVLen() / SEW;
18542 // Helper to find Masked Pseudo instruction from MC instruction, LMUL and SEW.
18544 lookupMaskedIntrinsic(uint16_t MCOpcode, RISCVII::VLMUL LMul, unsigned SEW) {
18546 RISCVVInversePseudosTable::getBaseInfo(MCOpcode, LMul, SEW);
18547 assert(Inverse && "Unexpected LMUL and SEW pair for instruction");
18550 assert(Masked && "Could not find masked instruction for LMUL and SEW pair");