Lines Matching defs:M1VT

4078     MVT M1VT = getContainerForFixedLengthVector(DAG, OneRegVT, Subtarget);
4079     assert(M1VT == getLMUL1VT(M1VT));
4086     unsigned NumOpElts = M1VT.getVectorMinNumElements();
4092       SubBV = convertToScalableVector(M1VT, SubBV, DAG, Subtarget);
5051   MVT M1VT = getContainerForFixedLengthVector(DAG, OneRegVT, Subtarget);
5052   assert(M1VT == getLMUL1VT(M1VT));
5053   unsigned NumOpElts = M1VT.getVectorMinNumElements();
5066     SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, SrcVec,
5070     SubVec = convertToScalableVector(M1VT, SubVec, DAG, Subtarget);
8487     const MVT M1VT = getLMUL1VT(ContainerVT);
8489         VLEN && ContainerVT.bitsGT(M1VT)) {
8495           SubRegIdx * M1VT.getVectorElementCount().getKnownMinValue();
8498       ContainerVT = M1VT;
8699     MVT M1VT = getLMUL1VT(ContainerVT);
8706       SubRegIdx * M1VT.getVectorElementCount().getKnownMinValue();
8707     Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, Vec,
8710     ContainerVT = M1VT;
9807   const MVT M1VT = getLMUL1VT(VecVT);
9813   auto InnerVT = VecVT.bitsLE(M1VT) ? VecVT : M1VT;
9820   if (M1VT != InnerVT)
9822         DAG.getNode(ISD::INSERT_SUBVECTOR, DL, M1VT, DAG.getUNDEF(M1VT),
9824   SDValue PassThru = NonZeroAVL ? DAG.getUNDEF(M1VT) : InitialValue;
9827   SDValue Reduction = DAG.getNode(RVVOpcode, DL, M1VT, Ops);
17510     const MVT M1VT = getLMUL1VT(VT);
17511     if (M1VT.bitsLT(VT)) {
17513           DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, Passthru,
17516           DAG.getNode(N->getOpcode(), DL, M1VT, M1Passthru, Scalar, VL);
17535     const MVT M1VT = getLMUL1VT(VecVT);
17536     if (M1VT.bitsLT(VecVT)) {
17537       Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, Vec,