Lines Matching defs:LMul

2475 unsigned RISCVTargetLowering::getRegClassIDForLMUL(RISCVII::VLMUL LMul) {
2476   switch (LMul) {
2664   unsigned LMul = divideCeil(VT.getSizeInBits(), MinVLen);
2666   if (LMul > Subtarget.getMaxLMULForFixedLengthVectors())
2860     unsigned LMul;
2862     std::tie(LMul, Fractional) =
2865       Cost = LMul <= DLenFactor ? (DLenFactor / LMul) : 1;
2867       Cost = (LMul * DLenFactor);
8977   SDValue LMul = DAG.getTargetConstant(VLMUL, DL, XLenVT);
8984       DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, XLenVT, ID, AVL, Sew, LMul);
17932       auto [LMul, Fractional] = RISCVVType::decodeVLMUL(VLMUL);
17934       MaxVL = (Fractional) ? MaxVL / LMul : MaxVL * LMul;
18544 lookupMaskedIntrinsic(uint16_t MCOpcode, RISCVII::VLMUL LMul, unsigned SEW) {
18546       RISCVVInversePseudosTable::getBaseInfo(MCOpcode, LMul, SEW);
18587   RISCVII::VLMUL LMul = RISCVII::getLMul(MI.getDesc().TSFlags);
18592       lookupMaskedIntrinsic(RISCV::VFCVT_F_X_V, LMul, 1 << Log2SEW)
22151 void RVVArgDispatcher::allocatePhysReg(unsigned NF, unsigned LMul,
22153   assert((StartReg % LMul) == 0 &&
22156   switch (LMul) {
22175       AllocatedPhysRegs.push_back(VRArrays[(StartReg - 8) / LMul + i]);