Lines Matching defs:SLLI
215 // See if we can create this constant as (ADD (SLLI X, C), X) where X is at
218 // If we have Zba we can use (ADD_UW X, (SLLI X, 32)) to handle cases where
227 SDValue SLLI = SDValue(
228 CurDAG->getMachineNode(RISCV::SLLI, DL, VT, Lo,
231 return SDValue(CurDAG->getMachineNode(AddOpc, DL, VT, Lo, SLLI), 0);
670 unsigned ShOpc = SignExt ? RISCV::SLLIW : RISCV::SLLI;
675 SDNode *SLLI =
678 ReplaceNode(Node, SLLI);
1093 SDNode *SLLI = CurDAG->getMachineNode(
1094 RISCV::SLLI, DL, VT, SDValue(SRLIW, 0),
1096 ReplaceNode(Node, SLLI);
1122 SDNode *SLLI = CurDAG->getMachineNode(
1123 RISCV::SLLI, DL, VT, SDValue(SRLIW, 0),
1125 ReplaceNode(Node, SLLI);
1166 SDNode *SLLI =
1167 CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0->getOperand(0),
1170 RISCV::SRLI, DL, VT, SDValue(SLLI, 0),
1200 SDNode *SLLI =
1201 CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0->getOperand(0),
1204 RISCV::SRAI, DL, VT, SDValue(SLLI, 0),
1318 SDNode *SLLI = CurDAG->getMachineNode(
1319 RISCV::SLLI, DL, VT, X,
1322 RISCV::SRLI, DL, VT, SDValue(SLLI, 0),
1348 SDNode *SLLI = CurDAG->getMachineNode(
1349 RISCV::SLLI, DL, VT, X,
1352 RISCV::SRLI, DL, VT, SDValue(SLLI, 0),
1378 SDNode *SLLI = CurDAG->getMachineNode(
1379 RISCV::SLLI, DL, VT, SDValue(SRLI, 0),
1381 ReplaceNode(Node, SLLI);
1390 SDNode *SLLI = CurDAG->getMachineNode(
1391 RISCV::SLLI, DL, VT, SDValue(SRLIW, 0),
1393 ReplaceNode(Node, SLLI);
1407 SDNode *SLLI = CurDAG->getMachineNode(
1408 RISCV::SLLI, DL, VT, SDValue(SRLI, 0),
1410 ReplaceNode(Node, SLLI);
1418 SDNode *SLLI = CurDAG->getMachineNode(
1419 RISCV::SLLI, DL, VT, SDValue(SRLIW, 0),
1421 ReplaceNode(Node, SLLI);
1425 // If we have 32 bits in the mask, we can use SLLI_UW instead of SLLI.
1482 // make it more costly to materialize. Otherwise, using a SLLI might allow
1519 SDNode *SLLI =
1520 CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0.getOperand(0),
1523 SDValue(SLLI, 0), SDValue(Imm, 0));
3040 // 32-ShAmt leading zeros and c2 trailing zeros. We can use SLLI by
3049 RISCV::SLLI, DL, VT, N0.getOperand(0),
3175 case RISCV::SLLI:
3176 // SLLI only uses the lower (XLen - ShAmt) bits.
3476 case RISCV::SLLI: {
3487 case RISCV::SLLI: Opc = RISCV::SLLIW; break;
3494 if (N0.getMachineOpcode() == RISCV::SLLI &&