Lines Matching defs:N0
613 SDValue N0 = Node->getOperand(0);
626 SDValue Shift = N0;
632 if (isInt<32>(Val) && N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
633 N0.hasOneUse() && cast<VTSDNode>(N0.getOperand(1))->getVT() == MVT::i32) {
635 Shift = N0.getOperand(0);
691 SDValue N0 = Node->getOperand(0);
692 if (!N0.hasOneUse())
695 auto BitfieldExtract = [&](SDValue N0, unsigned Msb, unsigned Lsb, SDLoc DL,
697 return CurDAG->getMachineNode(RISCV::TH_EXT, DL, VT, N0.getOperand(0),
708 if (N0.getOpcode() == ISD::SHL) {
709 auto *N01C = dyn_cast<ConstantSDNode>(N0->getOperand(1));
723 SDNode *TH_EXT = BitfieldExtract(N0, Msb, Lsb, DL, VT);
730 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
732 cast<VTSDNode>(N0.getOperand(1))->getVT().getSizeInBits();
741 SDNode *TH_EXT = BitfieldExtract(N0, Msb, Lsb, DL, VT);
1076 SDValue N0 = Node->getOperand(0);
1077 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse() ||
1078 !isa<ConstantSDNode>(N0.getOperand(1)))
1081 uint64_t Mask = N0.getConstantOperandVal(1);
1091 RISCV::SRLIW, DL, VT, N0->getOperand(0),
1106 SDValue N0 = Node->getOperand(0);
1107 if (N0.getOpcode() != ISD::AND || !isa<ConstantSDNode>(N0.getOperand(1)))
1110 uint64_t Mask = N0.getConstantOperandVal(1);
1114 if (isShiftedMask_64(Mask) && N0.hasOneUse()) {
1120 RISCV::SRLIW, DL, VT, N0->getOperand(0),
1147 N0->getOperand(0), CurDAG->getTargetConstant(ShAmt, DL, VT));
1153 if (!N0.hasOneUse())
1160 N0->getOperand(0), CurDAG->getTargetConstant(ShAmt, DL, VT));
1167 CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0->getOperand(0),
1190 SDValue N0 = Node->getOperand(0);
1191 if (N0.getOpcode() != ISD::SIGN_EXTEND_INREG || !N0.hasOneUse())
1195 cast<VTSDNode>(N0.getOperand(1))->getVT().getSizeInBits();
1201 CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0->getOperand(0),
1223 SDValue N0 = Node->getOperand(0);
1238 bool LeftShift = N0.getOpcode() == ISD::SHL;
1239 if (LeftShift || N0.getOpcode() == ISD::SRL) {
1240 auto *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1263 bool OneUseOrZExtW = N0.hasOneUse() || C1 == UINT64_C(0xFFFFFFFF);
1265 SDValue X = N0.getOperand(0);
1285 if (C2 >= 32 && (Leading - C2) == 1 && N0.hasOneUse() &&
1447 if (tryUnsignedBitfieldExtract(Node, DL, VT, N0, Msb, 0))
1469 SDValue N0 = Node->getOperand(0);
1470 if (N0.getOpcode() != ISD::AND || !isa<ConstantSDNode>(N0.getOperand(1)))
1473 uint64_t C2 = N0.getConstantOperandVal(1);
1489 if (IsANDIOrZExt && (isInt<12>(N1C->getSExtValue()) || !N0.hasOneUse()))
1496 if (IsZExtW && (isInt<32>(N1C->getSExtValue()) || !N0.hasOneUse()))
1520 CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0.getOperand(0),
2893 SDValue N0 = N.getOperand(0);
2894 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
2896 N0.getConstantOperandVal(1) == ShiftAmt)
2897 return N0.getOperand(0);
2935 SDValue N0 = N.getOperand(0);
2937 bool LeftShift = N0.getOpcode() == ISD::SHL;
2938 if ((LeftShift || N0.getOpcode() == ISD::SRL) &&
2939 isa<ConstantSDNode>(N0.getOperand(1))) {
2941 unsigned C2 = N0.getConstantOperandVal(1);
2959 RISCV::SRLI, DL, VT, N0.getOperand(0),
2972 RISCV::SRLI, DL, VT, N0.getOperand(0),
2984 SDValue N0 = N.getOperand(0);
2985 if (N0.getOpcode() == ISD::AND && N0.hasOneUse() &&
2986 isa<ConstantSDNode>(N0.getOperand(1))) {
2987 uint64_t Mask = N0.getConstantOperandVal(1);
3000 RISCV::SRLIW, DL, VT, N0.getOperand(0),
3012 RISCV::SRLIW, DL, VT, N0.getOperand(0),
3031 SDValue N0 = N.getOperand(0);
3032 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
3033 N0.hasOneUse()) {
3035 unsigned C2 = N0.getConstantOperandVal(1);
3049 RISCV::SLLI, DL, VT, N0.getOperand(0),
3465 SDValue N0 = N->getOperand(0);
3466 if (!N0.isMachineOpcode())
3469 switch (N0.getMachineOpcode()) {
3480 switch (N0.getMachineOpcode()) {
3490 SDValue N00 = N0.getOperand(0);
3491 SDValue N01 = N0.getOperand(1);
3494 if (N0.getMachineOpcode() == RISCV::SLLI &&
3514 if (N0.getValueType() == MVT::i32)
3519 ReplaceUses(N, N0.getNode());