Lines Matching defs:IsMasked

295     bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl<SDValue> &Operands,
308   if (IsMasked) {
328     if (IsMasked)
339 void RISCVDAGToDAGISel::selectVLSEG(SDNode *Node, bool IsMasked,
356   addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, IsStrided,
360       RISCV::getVLSEGPseudo(NF, IsMasked, IsStrided, /*FF*/ false, Log2SEW,
379 void RISCVDAGToDAGISel::selectVLSEGFF(SDNode *Node, bool IsMasked) {
396   addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked,
401       RISCV::getVLSEGPseudo(NF, IsMasked, /*Strided*/ false, /*FF*/ true,
421 void RISCVDAGToDAGISel::selectVLXSEG(SDNode *Node, bool IsMasked,
439   addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked,
453       NF, IsMasked, IsOrdered, IndexLog2EEW, static_cast<unsigned>(LMUL),
472 void RISCVDAGToDAGISel::selectVSSEG(SDNode *Node, bool IsMasked,
478   if (IsMasked)
490   addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, IsStrided,
494       NF, IsMasked, IsStrided, Log2SEW, static_cast<unsigned>(LMUL));
504 void RISCVDAGToDAGISel::selectVSXSEG(SDNode *Node, bool IsMasked,
508   if (IsMasked)
521   addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked,
535       NF, IsMasked, IsOrdered, IndexLog2EEW, static_cast<unsigned>(LMUL),
1790       selectVLSEG(Node, /*IsMasked*/ false, /*IsStrided*/ false);
1800       selectVLSEG(Node, /*IsMasked*/ true, /*IsStrided*/ false);
1810       selectVLSEG(Node, /*IsMasked*/ false, /*IsStrided*/ true);
1820       selectVLSEG(Node, /*IsMasked*/ true, /*IsStrided*/ true);
1830       selectVLXSEG(Node, /*IsMasked*/ false, /*IsOrdered*/ true);
1839       selectVLXSEG(Node, /*IsMasked*/ false, /*IsOrdered*/ false);
1848       selectVLXSEG(Node, /*IsMasked*/ true, /*IsOrdered*/ true);
1857       selectVLXSEG(Node, /*IsMasked*/ true, /*IsOrdered*/ false);
1866       selectVLSEGFF(Node, /*IsMasked*/ false);
1876       selectVLSEGFF(Node, /*IsMasked*/ true);
1883       bool IsMasked = IntNo == Intrinsic::riscv_vloxei_mask ||
1896       addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked,
1911           IsMasked, IsOrdered, IndexLog2EEW, static_cast<unsigned>(LMUL),
1927       bool IsMasked = IntNo == Intrinsic::riscv_vle_mask ||
1953       addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, IsStrided,
1958           RISCV::getVLEPseudo(IsMasked, IsStrided, /*FF*/ false, Log2SEW,
1971       bool IsMasked = IntNo == Intrinsic::riscv_vleff_mask;
1979       addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked,
1985           RISCV::getVLEPseudo(IsMasked, /*Strided*/ false, /*FF*/ true,
2008       selectVSSEG(Node, /*IsMasked*/ false, /*IsStrided*/ false);
2018       selectVSSEG(Node, /*IsMasked*/ true, /*IsStrided*/ false);
2028       selectVSSEG(Node, /*IsMasked*/ false, /*IsStrided*/ true);
2038       selectVSSEG(Node, /*IsMasked*/ true, /*IsStrided*/ true);
2048       selectVSXSEG(Node, /*IsMasked*/ false, /*IsOrdered*/ true);
2057       selectVSXSEG(Node, /*IsMasked*/ false, /*IsOrdered*/ false);
2066       selectVSXSEG(Node, /*IsMasked*/ true, /*IsOrdered*/ true);
2075       selectVSXSEG(Node, /*IsMasked*/ true, /*IsOrdered*/ false);
2081       bool IsMasked = IntNo == Intrinsic::riscv_vsoxei_mask ||
2094       addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked,
2109           IsMasked, IsOrdered, IndexLog2EEW,
2125       bool IsMasked = IntNo == Intrinsic::riscv_vse_mask ||
2137       addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, IsStrided,
2142           IsMasked, IsStrided, Log2SEW, static_cast<unsigned>(LMUL));
2335         /*IsMasked*/ false, IsStrided, /*FF*/ false,
3748   bool IsMasked = false;
3753     IsMasked = true;
3755   assert(!(IsMasked && !HasTiedDest) && "Expected tied dest");
3770   if (IsMasked && Mask) {
3850   if (TrueVL != VL || !IsMasked)
3859   if (IsMasked) {
3909   const unsigned NormalOpsEnd = TrueVLIndex - IsMasked - HasRoundingMode;
3910   assert(!IsMasked || NormalOpsEnd == Info->MaskOpIdx);