Lines Matching defs:MBBI
45 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
47 bool expandCCOp(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
49 bool expandVSetVL(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
51 MachineBasicBlock::iterator MBBI, unsigned Opcode);
53 MachineBasicBlock::iterator MBBI);
55 MachineBasicBlock::iterator MBBI);
91 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
92 while (MBBI != E) {
93 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
94 Modified |= expandMI(MBB, MBBI, NMBBI);
95 MBBI = NMBBI;
102 MachineBasicBlock::iterator MBBI,
107 switch (MBBI->getOpcode()) {
109 return expandRV32ZdinxStore(MBB, MBBI);
111 return expandRV32ZdinxLoad(MBB, MBBI);
141 return expandCCOp(MBB, MBBI, NextMBBI);
145 return expandVSetVL(MBB, MBBI);
154 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXOR_MM);
163 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
170 MachineBasicBlock::iterator MBBI,
174 MachineInstr &MI = *MBBI;
190 BuildMI(MBB, MBBI, DL, TII->getBrCond(CC))
262 MachineBasicBlock::iterator MBBI) {
263 assert(MBBI->getNumExplicitOperands() == 3 && MBBI->getNumOperands() >= 5 &&
266 DebugLoc DL = MBBI->getDebugLoc();
268 assert((MBBI->getOpcode() == RISCV::PseudoVSETVLI ||
269 MBBI->getOpcode() == RISCV::PseudoVSETVLIX0 ||
270 MBBI->getOpcode() == RISCV::PseudoVSETIVLI) &&
273 if (MBBI->getOpcode() == RISCV::PseudoVSETIVLI)
280 Register DstReg = MBBI->getOperand(0).getReg();
281 bool DstIsDead = MBBI->getOperand(0).isDead();
282 BuildMI(MBB, MBBI, DL, Desc)
284 .add(MBBI->getOperand(1)) // VL
285 .add(MBBI->getOperand(2)); // VType
287 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
292 MachineBasicBlock::iterator MBBI,
294 DebugLoc DL = MBBI->getDebugLoc();
295 Register DstReg = MBBI->getOperand(0).getReg();
297 BuildMI(MBB, MBBI, DL, Desc, DstReg)
300 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
308 MachineBasicBlock::iterator MBBI) {
309 DebugLoc DL = MBBI->getDebugLoc();
312 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
314 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
316 assert(MBBI->hasOneMemOperand() && "Expected mem operand");
317 MachineMemOperand *OldMMO = MBBI->memoperands().front();
322 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
323 .addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
324 .addReg(MBBI->getOperand(1).getReg())
325 .add(MBBI->getOperand(2))
328 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
332 assert(MBBI->getOperand(2).getOffset() % 8 == 0);
333 MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
334 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
335 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
336 .add(MBBI->getOperand(1))
337 .add(MBBI->getOperand(2))
340 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
341 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
342 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
343 .add(MBBI->getOperand(1))
344 .addImm(MBBI->getOperand(2).getImm() + 4)
347 MBBI->eraseFromParent();
355 MachineBasicBlock::iterator MBBI) {
356 DebugLoc DL = MBBI->getDebugLoc();
359 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
361 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
363 assert(MBBI->hasOneMemOperand() && "Expected mem operand");
364 MachineMemOperand *OldMMO = MBBI->memoperands().front();
371 bool IsOp1EqualToLo = Lo == MBBI->getOperand(1).getReg();
374 BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
375 .addReg(MBBI->getOperand(1).getReg())
376 .add(MBBI->getOperand(2))
380 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
381 auto Offset = MBBI->getOperand(2).getOffset();
382 assert(MBBI->getOperand(2).getOffset() % 8 == 0);
383 MBBI->getOperand(2).setOffset(Offset + 4);
384 BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
385 .addReg(MBBI->getOperand(1).getReg())
386 .add(MBBI->getOperand(2))
388 MBBI->getOperand(2).setOffset(Offset);
390 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
391 BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
392 .addReg(MBBI->getOperand(1).getReg())
393 .addImm(MBBI->getOperand(2).getImm() + 4)
399 BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
400 .addReg(MBBI->getOperand(1).getReg())
401 .add(MBBI->getOperand(2))
405 MBBI->eraseFromParent();
429 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
432 MachineBasicBlock::iterator MBBI,
436 MachineBasicBlock::iterator MBBI,
439 MachineBasicBlock::iterator MBBI,
442 MachineBasicBlock::iterator MBBI,
445 MachineBasicBlock::iterator MBBI,
448 MachineBasicBlock::iterator MBBI,
486 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
487 while (MBBI != E) {
488 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
489 Modified |= expandMI(MBB, MBBI, NMBBI);
490 MBBI = NMBBI;
497 MachineBasicBlock::iterator MBBI,
500 switch (MBBI->getOpcode()) {
502 return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
504 return expandLoadGlobalAddress(MBB, MBBI, NextMBBI);
506 return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
508 return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
510 return expandLoadTLSDescAddress(MBB, MBBI, NextMBBI);
516 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
520 MachineInstr &MI = *MBBI;
532 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
536 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
548 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
550 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
555 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
558 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
563 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
566 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
571 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
573 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
578 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
581 MachineInstr &MI = *MBBI;
598 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
601 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
605 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), RISCV::X10)
609 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoTLSDESCCall), RISCV::X5)
614 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), FinalReg)