Lines Matching +full:ouput +full:- +full:only
1 //===-- RISCVAsmPrinter.cpp - RISC-V LLVM assembly writer -----------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // of machine-dependent LLVM code to the RISC-V assembly language.
12 //===----------------------------------------------------------------------===//
47 #define DEBUG_TYPE "asm-printer"
50 "Number of RISC-V Compressed instructions emitted");
65 StringRef getPassName() const override { return "RISC-V Assembly Printer"; }
116 unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4;
132 if (MII == MBB.end() || MII->isCall() ||
133 MII->getOpcode() == RISCV::DBG_VALUE ||
134 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
135 MII->getOpcode() == TargetOpcode::STACKMAP)
138 NumNOPBytes -= 4;
149 unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4;
191 assert((NumBytes - EncodedBytes) % NOPBytes == 0 &&
193 emitNops((NumBytes - EncodedBytes) / NOPBytes);
198 unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4;
251 // Simple pseudo-instructions have their lowering (with expansion to real
252 // instructions) auto-generated.
258 if (!STI->hasStdExtZihintntl())
261 if (MI->memoperands_empty())
264 MachineMemOperand *MMO = *(MI->memoperands_begin());
265 if (!MMO->isNonTemporal())
269 if (MMO->getFlags() & MONontemporalBit0)
271 if (MMO->getFlags() & MONontemporalBit1)
275 if (STI->hasStdExtCOrZca() && STI->enableRVCHintInstrs())
288 RISCV_MC::verifyInstructionPredicates(MI->getOpcode(),
293 // Do any auto-generated pseudo lowerings.
298 switch (MI->getOpcode()) {
329 const MachineOperand &MO = MI->getOperand(OpNo);
362 Sym->print(OS, MAI);
379 const MachineOperand &AddrReg = MI->getOperand(OpNo);
380 assert(MI->getNumOperands() > OpNo + 1 && "Expected additional operand");
381 const MachineOperand &Offset = MI->getOperand(OpNo + 1);
404 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
408 if (STI->hasFeature(Feature.Value) == MCSTI.hasFeature(Feature.Value))
414 auto Delta = STI->hasFeature(Feature.Value) ? RISCVOptionArchArgType::Plus
430 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
444 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
446 dyn_cast_or_null<MDString>(M.getModuleFlag("target-abi")))
447 RTS.setTargetABI(RISCVABI::getTargetABI(ModuleTargetABI->getString()));
452 if (auto *MD = dyn_cast_or_null<MDNode>(M.getModuleFlag("riscv-isa"))) {
453 for (auto &ISA : MD->operands()) {
456 ISAString->getString(), /*EnableExperimentalExtension=*/true,
461 if (ISAInfo->hasExtension(Feature.Key) &&
478 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
487 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
495 const auto *RMFI = MF->getInfo<RISCVMachineFunctionInfo>();
496 if (RMFI->isVectorCall()) {
498 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
516 // FIXME: Make this work on non-ELF.
518 report_fatal_error("llvm.hwasan.check.memaccess only supported on ELF");
520 std::string SymName = "__hwasan_check_x" + utostr(Reg - RISCV::X0) + "_" +
532 assert(std::next(MI.getIterator())->isCall() &&
534 assert(std::next(MI.getIterator())->getOperand(0).getReg() == AddrReg &&
540 // call. The check defaults to X6/X7, but can fall back to X28-X31 if
545 return Reg != AddrReg && !STI->isRegisterReservedByUser(Reg);
565 // Adjust the offset for patchable-function-prefix. This assumes that
566 // patchable-function-prefix is the same for all functions.
567 int NopSize = STI->hasStdExtCOrZca() ? 2 : 4;
570 ->getFunction()
571 .getFnAttribute("patchable-function-prefix")
579 .addImm(-(PrefixNops * NopSize + 4)));
582 // Load the expected 32-bit type hash.
593 MCInstBuilder((STI->hasFeature(RISCV::Feature64Bit) && Hi20)
610 OutStreamer->emitLabel(Trap);
613 OutStreamer->emitLabel(Pass);
629 // run-time linkers can instead eagerly bind this function.
631 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
646 OutStreamer->switchSection(OutContext.getELFSection(
648 ELF::SHF_EXECINSTR | ELF::SHF_ALLOC | ELF::SHF_GROUP, 0, Sym->getName(),
651 OutStreamer->emitSymbolAttribute(Sym, MCSA_ELF_TypeFunction);
652 OutStreamer->emitSymbolAttribute(Sym, MCSA_Weak);
653 OutStreamer->emitSymbolAttribute(Sym, MCSA_Hidden);
654 OutStreamer->emitLabel(Sym);
657 OutStreamer->emitInstruction(
660 OutStreamer->emitInstruction(MCInstBuilder(RISCV::SRLI)
666 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADD)
671 OutStreamer->emitInstruction(
675 OutStreamer->emitInstruction(
680 OutStreamer->emitInstruction(
688 OutStreamer->emitLabel(ReturnSym);
689 OutStreamer->emitInstruction(MCInstBuilder(RISCV::JALR)
694 OutStreamer->emitLabel(HandleMismatchOrPartialSym);
696 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
702 OutStreamer->emitInstruction(
709 OutStreamer->emitInstruction(
714 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
717 .addImm(Size - 1),
719 OutStreamer->emitInstruction(
726 OutStreamer->emitInstruction(
729 OutStreamer->emitInstruction(
732 OutStreamer->emitInstruction(
739 OutStreamer->emitLabel(HandleMismatchSym);
742 // +=================================+ <-- [SP + 256]
745 // | Stack frame space for x12 - x31.|
748 // +---------------------------------+ <-- [SP + 96]
751 // +---------------------------------+ <-- [SP + 88]
754 // +---------------------------------+ <-- [SP + 80]
757 // +---------------------------------+ <-- [SP + 72]
761 // +---------------------------------+ <-- [SP + 64]
764 // | Stack frame space for x2 - x7. |
767 // +---------------------------------+ <-- [SP + 16]
770 // +---------------------------------+ <-- [SP + 8]
773 // +---------------------------------+ <-- [x2 / SP]
776 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
779 .addImm(-256),
783 OutStreamer->emitInstruction(MCInstBuilder(RISCV::SD)
789 OutStreamer->emitInstruction(MCInstBuilder(RISCV::SD)
796 OutStreamer->emitInstruction(
801 OutStreamer->emitInstruction(
806 OutStreamer->emitInstruction(MCInstBuilder(RISCV::ADDI)
811 OutStreamer->emitInstruction(
818 OutStreamer->emitInstruction(MCInstBuilder(RISCV::PseudoCALL).addExpr(Expr),
911 MCOp = lowerSymbolOperand(MO, MO.getMBB()->getSymbol(), *this);
940 RISCVVPseudosTable::getPseudoInfo(MI->getOpcode());
944 OutMI.setOpcode(RVV->BaseInstr);
946 const MachineBasicBlock *MBB = MI->getParent();
948 const MachineFunction *MF = MBB->getParent();
951 const RISCVSubtarget &Subtarget = MF->getSubtarget<RISCVSubtarget>();
956 const MCInstrDesc &MCID = MI->getDesc();
958 unsigned NumOps = MI->getNumExplicitOperands();
963 --NumOps;
965 --NumOps;
967 --NumOps;
969 --NumOps;
973 const MachineOperand &MO = MI->getOperand(OpNo);
974 // Skip vl ouput. It should be the second output.
979 if (OpNo == MI->getNumExplicitDefs() && MO.isReg() && MO.isTied()) {
982 const MCInstrDesc &OutMCID = TII->get(OutMI.getOpcode());
1001 Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
1005 TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass);
1008 Reg = TRI->getSubReg(Reg, RISCV::sub_32);
1021 Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
1037 const MCInstrDesc &OutMCID = TII->get(OutMI.getOpcode());
1041 "Expected only mask operand to be missing");
1053 OutMI.setOpcode(MI->getOpcode());
1055 for (const MachineOperand &MO : MI->operands()) {
1063 const Function &F = MI->getParent()->getParent()->getFunction();
1064 if (F.hasFnAttribute("patchable-function-entry")) {
1066 if (F.getFnAttribute("patchable-function-entry")