Lines Matching defs:OutMI

110   bool lowerToMCInst(const MachineInstr *MI, MCInst &OutMI);
938                                             MCInst &OutMI) {
944   OutMI.setOpcode(RVV->BaseInstr);
982       const MCInstrDesc &OutMCID = TII->get(OutMI.getOpcode());
983       // Skip if the next operand in OutMI is not supposed to be tied. Unless it
985       if (OutMCID.getOperandConstraint(OutMI.getNumOperands(), MCOI::TIED_TO) <
1032     OutMI.addOperand(MCOp);
1037   const MCInstrDesc &OutMCID = TII->get(OutMI.getOpcode());
1038   if (OutMI.getNumOperands() < OutMCID.getNumOperands()) {
1039     assert(OutMCID.operands()[OutMI.getNumOperands()].RegClass ==
1042     OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister));
1045   assert(OutMI.getNumOperands() == OutMCID.getNumOperands());
1049 bool RISCVAsmPrinter::lowerToMCInst(const MachineInstr *MI, MCInst &OutMI) {
1050   if (lowerRISCVVMachineInstrToMCInst(MI, OutMI))
1053   OutMI.setOpcode(MI->getOpcode());
1058       OutMI.addOperand(MCOp);
1061   switch (OutMI.getOpcode()) {