Lines Matching +full:use +full:- +full:case
1 //===-- RISCVRegisterBankInfo.cpp -------------------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 /// This file implements the targeting of the RegisterBankInfo class for RISC-V.
11 //===----------------------------------------------------------------------===//
29 // clang-format off
39 // clang-format on
121 case RISCV::GPRRegClassID:
122 case RISCV::GPRF16RegClassID:
123 case RISCV::GPRF32RegClassID:
124 case RISCV::GPRNoX0RegClassID:
125 case RISCV::GPRNoX0X2RegClassID:
126 case RISCV::GPRJALRRegClassID:
127 case RISCV::GPRJALRNonX7RegClassID:
128 case RISCV::GPRTCRegClassID:
129 case RISCV::GPRTCNonX7RegClassID:
130 case RISCV::GPRC_and_GPRTCRegClassID:
131 case RISCV::GPRCRegClassID:
132 case RISCV::GPRC_and_SR07RegClassID:
133 case RISCV::SR07RegClassID:
134 case RISCV::SPRegClassID:
135 case RISCV::GPRX0RegClassID:
137 case RISCV::FPR64RegClassID:
138 case RISCV::FPR16RegClassID:
139 case RISCV::FPR32RegClassID:
140 case RISCV::FPR64CRegClassID:
141 case RISCV::FPR32CRegClassID:
143 case RISCV::VMRegClassID:
144 case RISCV::VRRegClassID:
145 case RISCV::VRNoV0RegClassID:
146 case RISCV::VRM2RegClassID:
147 case RISCV::VRM2NoV0RegClassID:
148 case RISCV::VRM4RegClassID:
149 case RISCV::VRM4NoV0RegClassID:
150 case RISCV::VMV0RegClassID:
151 case RISCV::VRM2_with_sub_vrm1_0_in_VMV0RegClassID:
152 case RISCV::VRM4_with_sub_vrm1_0_in_VMV0RegClassID:
153 case RISCV::VRM8RegClassID:
154 case RISCV::VRM8NoV0RegClassID:
155 case RISCV::VRM8_with_sub_vrm1_0_in_VMV0RegClassID:
165 case 16:
168 case 32:
171 case 64:
197 case TargetOpcode::G_FPTOSI:
198 case TargetOpcode::G_FPTOUI:
199 case TargetOpcode::G_FCMP:
212 case TargetOpcode::G_SITOFP:
213 case TargetOpcode::G_UITOFP:
251 // Try the default logic for non-generic instructions that are either copies
259 const MachineFunction &MF = *MI.getParent()->getParent();
273 case TargetOpcode::G_ADD:
274 case TargetOpcode::G_SUB:
275 case TargetOpcode::G_SHL:
276 case TargetOpcode::G_ASHR:
277 case TargetOpcode::G_LSHR:
278 case TargetOpcode::G_AND:
279 case TargetOpcode::G_OR:
280 case TargetOpcode::G_XOR:
281 case TargetOpcode::G_MUL:
282 case TargetOpcode::G_SDIV:
283 case TargetOpcode::G_SREM:
284 case TargetOpcode::G_SMULH:
285 case TargetOpcode::G_SMAX:
286 case TargetOpcode::G_SMIN:
287 case TargetOpcode::G_UDIV:
288 case TargetOpcode::G_UREM:
289 case TargetOpcode::G_UMULH:
290 case TargetOpcode::G_UMAX:
291 case TargetOpcode::G_UMIN:
292 case TargetOpcode::G_PTR_ADD:
293 case TargetOpcode::G_PTRTOINT:
294 case TargetOpcode::G_INTTOPTR:
295 case TargetOpcode::G_FADD:
296 case TargetOpcode::G_FSUB:
297 case TargetOpcode::G_FMUL:
298 case TargetOpcode::G_FDIV:
299 case TargetOpcode::G_FABS:
300 case TargetOpcode::G_FNEG:
301 case TargetOpcode::G_FSQRT:
302 case TargetOpcode::G_FMAXNUM:
303 case TargetOpcode::G_FMINNUM: {
329 case TargetOpcode::G_SEXTLOAD:
330 case TargetOpcode::G_ZEXTLOAD:
333 case TargetOpcode::G_IMPLICIT_DEF: {
338 // FIXME: May need to do a better job determining when to use FPRB.
339 // For example, the look through COPY case:
356 case TargetOpcode::G_LOAD: {
360 // Use FPR64 for s64 loads on rv32.
368 // In that case, we want the default mapping to be on FPR
371 // If we have at least one direct use in a FP instruction,
379 case TargetOpcode::G_STORE: {
383 // Use FPR64 for s64 stores on rv32.
395 case TargetOpcode::G_SELECT: {
414 // Use FPR64 for s64 select on rv32.
462 case TargetOpcode::G_FPTOSI:
463 case TargetOpcode::G_FPTOUI:
464 case RISCV::G_FCLASS: {
470 case TargetOpcode::G_SITOFP:
471 case TargetOpcode::G_UITOFP: {
477 case TargetOpcode::G_FCMP: {
486 case TargetOpcode::G_MERGE_VALUES: {
487 // Use FPR64 for s64 merge on rv32.
497 case TargetOpcode::G_UNMERGE_VALUES: {
498 // Use FPR64 for s64 unmerge on rv32.