Lines Matching full:mib
61 void preISelLower(MachineInstr &MI, MachineIRBuilder &MIB,
64 bool replacePtrWithInt(MachineOperand &Op, MachineIRBuilder &MIB,
69 bool selectImplicitDef(MachineInstr &MI, MachineIRBuilder &MIB,
71 bool materializeImm(Register Reg, int64_t Imm, MachineIRBuilder &MIB) const;
72 bool selectAddr(MachineInstr &MI, MachineIRBuilder &MIB,
75 bool selectSExtInreg(MachineInstr &MI, MachineIRBuilder &MIB) const;
76 bool selectSelect(MachineInstr &MI, MachineIRBuilder &MIB,
78 bool selectFPCompare(MachineInstr &MI, MachineIRBuilder &MIB,
81 MachineIRBuilder &MIB) const;
82 bool selectMergeValues(MachineInstr &MI, MachineIRBuilder &MIB,
84 bool selectUnmergeValues(MachineInstr &MI, MachineIRBuilder &MIB,
104 void renderNegImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
106 void renderImmSubFromXLen(MachineInstrBuilder &MIB, const MachineInstr &MI,
108 void renderImmSubFrom32(MachineInstrBuilder &MIB, const MachineInstr &MI,
110 void renderImmPlus1(MachineInstrBuilder &MIB, const MachineInstr &MI,
112 void renderImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
115 void renderTrailingZeros(MachineInstrBuilder &MIB, const MachineInstr &MI,
220 return {{[=](MachineInstrBuilder &MIB) {
221 MachineIRBuilder(*MIB.getInstr())
223 MIB.addReg(ShAmtReg);
230 return {{[=](MachineInstrBuilder &MIB) {
231 MachineIRBuilder(*MIB.getInstr())
234 MIB.addReg(ShAmtReg);
239 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(ShAmtReg); }}};
279 return {{[=](MachineInstrBuilder &MIB) {
280 MachineIRBuilder(*MIB.getInstr())
283 MIB.addReg(DstReg);
291 return {{[=](MachineInstrBuilder &MIB) {
292 MachineIRBuilder(*MIB.getInstr())
295 MIB.addReg(DstReg);
330 return {{[=](MachineInstrBuilder &MIB) {
331 MachineIRBuilder(*MIB.getInstr())
334 MIB.addReg(DstReg);
369 return {{[=](MachineInstrBuilder &MIB) {
370 MachineIRBuilder(*MIB.getInstr())
373 MIB.addReg(DstReg);
393 [=](MachineInstrBuilder &MIB) { MIB.add(RootDef->getOperand(1)); },
394 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); },
408 [=](MachineInstrBuilder &MIB) { MIB.add(LHSDef->getOperand(1)); },
409 [=](MachineInstrBuilder &MIB) { MIB.addImm(RHSC); },
412 return {{[=](MachineInstrBuilder &MIB) { MIB.add(LHS); },
413 [=](MachineInstrBuilder &MIB) { MIB.addImm(RHSC); }}};
419 return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); },
420 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }}};
513 MachineIRBuilder MIB(MI);
515 preISelLower(MI, MIB, MRI);
567 if (!materializeImm(DstReg, Imm, MIB))
582 if (!materializeImm(GPRReg, Imm.getSExtValue(), MIB))
588 auto FMV = MIB.buildInstr(Opcode, {DstReg}, {GPRReg});
598 MIB))
600 if (!materializeImm(GPRRegLow, Imm.trunc(32).getSExtValue(), MIB))
602 MachineInstrBuilder PairF64 = MIB.buildInstr(
618 return selectAddr(MI, MIB, MRI, GV->isDSOLocal(),
623 return selectAddr(MI, MIB, MRI);
629 auto Bcc = MIB.buildInstr(RISCVCC::getBrCond(CC), {}, {LHS, RHS})
647 MIB.buildInstr(RISCV::SLLI, {&RISCV::GPRRegClass}, {MI.getOperand(2)})
653 auto ADD = MIB.buildInstr(RISCV::ADD, {&RISCV::GPRRegClass},
660 MIB.buildInstr(LdOpc, {&RISCV::GPRRegClass}, {ADD.getReg(0)})
672 Dest = MIB.buildInstr(RISCV::ADD, {&RISCV::GPRRegClass},
679 MIB.buildInstr(RISCV::PseudoBRIND, {}, {Dest.getReg(0)}).addImm(0);
691 return selectSExtInreg(MI, MIB);
701 return selectSelect(MI, MIB, MRI);
703 return selectFPCompare(MI, MIB, MRI);
709 emitFence(FenceOrdering, FenceSSID, MIB);
714 return selectImplicitDef(MI, MIB, MRI);
716 return selectMergeValues(MI, MIB, MRI);
718 return selectUnmergeValues(MI, MIB, MRI);
725 MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI) const {
741 MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI) const {
757 MachineIRBuilder &MIB,
763 auto PtrToInt = MIB.buildPtrToInt(sXLen, PtrReg);
770 MachineIRBuilder &MIB,
777 replacePtrWithInt(MI.getOperand(1), MIB, MRI);
785 replacePtrWithInt(MI.getOperand(1), MIB, MRI);
792 void RISCVInstructionSelector::renderNegImm(MachineInstrBuilder &MIB,
798 MIB.addImm(-CstVal);
801 void RISCVInstructionSelector::renderImmSubFromXLen(MachineInstrBuilder &MIB,
807 MIB.addImm(STI.getXLen() - CstVal);
810 void RISCVInstructionSelector::renderImmSubFrom32(MachineInstrBuilder &MIB,
816 MIB.addImm(32 - CstVal);
819 void RISCVInstructionSelector::renderImmPlus1(MachineInstrBuilder &MIB,
825 MIB.addImm(CstVal + 1);
828 void RISCVInstructionSelector::renderImm(MachineInstrBuilder &MIB,
834 MIB.addImm(CstVal);
837 void RISCVInstructionSelector::renderTrailingZeros(MachineInstrBuilder &MIB,
843 MIB.addImm(llvm::countr_zero(C));
915 MachineInstr &MI, MachineIRBuilder &MIB, MachineRegisterInfo &MRI) const {
934 MachineIRBuilder &MIB) const {
935 MachineRegisterInfo &MRI = *MIB.getMRI();
938 MIB.buildCopy(DstReg, Register(RISCV::X0));
957 Result = MIB.buildInstr(I.getOpcode(), {TmpReg}, {})
962 Result = MIB.buildInstr(I.getOpcode(), {TmpReg},
966 Result = MIB.buildInstr(I.getOpcode(), {TmpReg}, {SrcReg, SrcReg});
970 MIB.buildInstr(I.getOpcode(), {TmpReg}, {SrcReg}).addImm(I.getImm());
984 MachineIRBuilder &MIB,
1022 auto Result = MIB.buildInstr(RISCV::PseudoLGA, {DefReg}, {})
1044 MachineInstr *AddrHi = MIB.buildInstr(RISCV::LUI, {AddrHiDest}, {})
1050 auto Result = MIB.buildInstr(RISCV::ADDI, {DefReg}, {AddrHiDest})
1076 auto Result = MIB.buildInstr(RISCV::PseudoLGA, {DefReg}, {})
1098 MachineIRBuilder &MIB) const {
1111 MIB.buildInstr(RISCV::ADDIW, {Dst.getReg()}, {Src.getReg()}).addImm(0U);
1121 MachineIRBuilder &MIB,
1138 MachineInstr *Result = MIB.buildInstr(Opc)
1202 MachineIRBuilder &MIB,
1221 auto Cmp = MIB.buildInstr(getFCmpOpcode(Pred, Size), {TmpReg}, {LHS, RHS});
1227 auto Cmp1 = MIB.buildInstr(getFCmpOpcode(CmpInst::FCMP_OLT, Size),
1231 auto Cmp2 = MIB.buildInstr(getFCmpOpcode(CmpInst::FCMP_OLT, Size),
1238 MIB.buildInstr(RISCV::OR, {TmpReg}, {Cmp1.getReg(0), Cmp2.getReg(0)});
1245 auto Cmp1 = MIB.buildInstr(getFCmpOpcode(CmpInst::FCMP_OEQ, Size),
1249 auto Cmp2 = MIB.buildInstr(getFCmpOpcode(CmpInst::FCMP_OEQ, Size),
1256 MIB.buildInstr(RISCV::AND, {TmpReg}, {Cmp1.getReg(0), Cmp2.getReg(0)});
1264 auto Xor = MIB.buildInstr(RISCV::XORI, {DstReg}, {TmpReg}).addImm(1);
1275 MachineIRBuilder &MIB) const {
1282 MIB.buildInstr(RISCV::FENCE, {}, {})
1289 MIB.buildInstr(TargetOpcode::MEMBARRIER, {}, {});
1297 MIB.buildInstr(TargetOpcode::MEMBARRIER, {}, {});
1309 MIB.buildInstr(RISCV::FENCE_TSO, {}, {});
1327 MIB.buildInstr(RISCV::FENCE, {}, {}).addImm(Pred).addImm(Succ);