Lines Matching +full:big +full:- +full:endian +full:- +full:desc
1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // Top-level implementation for the PowerPC target.
11 //===----------------------------------------------------------------------===//
56 EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden,
57 cl::desc("enable coalescing of duplicate branches for PPC"));
59 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
60 cl::desc("Disable CTR loops for PPC"));
63 opt<bool> DisableInstrFormPrep("disable-ppc-instr-form-prep", cl::Hidden,
64 cl::desc("Disable PPC loop instr form prep"));
67 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
68 cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
71 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
72 cl::desc("Disable VSX Swap Removal for PPC"));
75 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
76 cl::desc("Disable machine peepholes for PPC"));
79 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
80 cl::desc("Enable optimizations on complex GEPs"),
84 EnablePrefetch("enable-ppc-prefetching",
85 cl::desc("enable software prefetching on PPC"),
89 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
90 cl::desc("Add extra TOC register dependencies"),
94 EnableMachineCombinerPass("ppc-machine-combiner",
95 cl::desc("Enable the machine combiner pass"),
99 ReduceCRLogical("ppc-reduce-cr-logicals",
100 cl::desc("Expand eligible cr-logical binary ops to branches"),
104 "ppc-merge-string-pool",
105 cl::desc("Merge all of the strings in a module into one pool"),
109 "enable-ppc-gen-scalar-mass", cl::init(false),
110 cl::desc("Enable lowering math functions to their corresponding MASS "
157 // Most PPC* platforms are big endian, PPC(64)LE is little endian.
168 Ret += "-p:32:32";
174 Ret += "-Fi64";
176 Ret += is64Bit ? "-Fi64" : "-Fi32";
178 Ret += "-Fn32";
183 Ret += "-i64:64";
187 Ret += "-n32:64";
189 Ret += "-n32";
193 // which is 256 and 512 bytes - way over aligned.
195 Ret += "-S128-v256:256:256-v512:512:512";
204 // Make sure 64-bit features are available when CPUname is generic
221 FullFS = "+invariant-function-descriptors," + FullFS;
223 FullFS = "+invariant-function-descriptors";
251 "Unknown target-abi option!");
275 // Big Endian PPC and AIX default to PIC.
310 const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
316 DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
318 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
320 DAG->addMutation(createPowerPCMacroFusionDAGMutation());
327 const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
334 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
336 DAG->addMutation(createPowerPCMacroFusionDAGMutation());
341 // string with what are (currently) non-function specific overrides as it goes
356 Endianness(isLittleEndianTriple(TT) ? Endian::LITTLE : Endian::BIG) {
364 Attribute CPUAttr = F.getFnAttribute("target-cpu");
365 Attribute TuneAttr = F.getFnAttribute("tune-cpu");
366 Attribute FSAttr = F.getFnAttribute("target-features");
380 bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
384 FS += FS.empty() ? "-hard-float" : ",-hard-float";
405 //===----------------------------------------------------------------------===//
407 //===----------------------------------------------------------------------===//
416 // At any optimization level above -O0 we use the Machine Scheduler and not
458 if (TM->getOptLevel() != CodeGenOptLevel::None)
462 // Lower generic MASSV routines to PowerPC subtarget-specific entries.
465 // Generate PowerPC target-specific entries for scalar math functions
467 if (TM->getOptLevel() == CodeGenOptLevel::Aggressive &&
469 TM->Options.PPCGenScalarMASSEntries = EnablePPCGenScalarMASSEntries;
477 if (TM->getOptLevel() >= CodeGenOptLevel::Default && EnableGEPOpt) {
539 // For little endian, remove where possible the vector swap instructions
541 if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
544 // Reduce the number of cr-logical ops.
547 // Target-specific peephole cleanups performed after instruction
562 // FIXME: We probably don't need to run these for -fPIE.
567 // however a stage-2 clang build fails without LiveVariables computed here.
606 assert(Endianness != Endian::NOT_DETECTED &&
608 return Endianness == Endian::LITTLE;
618 PPCPreRASchedRegistry("ppc-prera",
623 PPCPostRASchedRegistry("ppc-postra",