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1 //===-- PPCScheduleE500mc.td - e500mc Scheduling Defs ------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the itinerary class data for the Freescale e500mc 32-bit
13 // Freescale Document Number E500MCRM, Rev. 1, 03/2012.
15 //===----------------------------------------------------------------------===//
21 def E500mc_DIS0 : FuncUnit; // Dispatch stage - insn 1
22 def E500mc_DIS1 : FuncUnit; // Dispatch stage - insn 2
27 // The CFX has a bypass path, allowing non-divide instructions to execute
30 def E500mc_SFX1 : FuncUnit; // Simple unit 1
46 InstrItinData<IIC_IntSimple, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
47 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
48 [4, 1, 1], // Latency = 1
51 InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
52 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
53 [4, 1, 1], // Latency = 1
56 InstrItinData<IIC_IntISEL, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
57 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
58 [4, 1, 1, 1], // Latency = 1
62 InstrItinData<IIC_IntCompare, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
63 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
64 [5, 1, 1], // Latency = 1 or 2
67 InstrItinData<IIC_IntDivW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
68 InstrStage<1, [E500mc_CFX_0], 0>,
70 [17, 1, 1], // Latency=4..35, Repeat= 4..35
73 InstrItinData<IIC_IntMFFS, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
77 InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
79 [11, 1, 1], // Latency = 8
81 InstrItinData<IIC_IntMulHW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
82 InstrStage<1, [E500mc_CFX_0]>],
83 [7, 1, 1], // Latency = 4, Repeat rate = 1
86 InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
87 InstrStage<1, [E500mc_CFX_0]>],
88 [7, 1, 1], // Latency = 4, Repeat rate = 1
91 InstrItinData<IIC_IntMulLI, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
92 InstrStage<1, [E500mc_CFX_0]>],
93 [7, 1, 1], // Latency = 4, Repeat rate = 1
96 InstrItinData<IIC_IntRotate, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
97 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
98 [4, 1, 1], // Latency = 1
101 InstrItinData<IIC_IntShift, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
102 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
103 [4, 1, 1], // Latency = 1
106 InstrItinData<IIC_IntTrapW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
108 [5, 1], // Latency = 2, Repeat rate = 2
110 InstrItinData<IIC_BrB, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
111 InstrStage<1, [E500mc_BU]>],
112 [4, 1], // Latency = 1
114 InstrItinData<IIC_BrCR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
115 InstrStage<1, [E500mc_BU]>],
116 [4, 1, 1], // Latency = 1
119 InstrItinData<IIC_BrMCR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
120 InstrStage<1, [E500mc_BU]>],
121 [4, 1], // Latency = 1
123 InstrItinData<IIC_BrMCRX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
124 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
125 [4, 1, 1], // Latency = 1
127 InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
128 InstrStage<1, [E500mc_LSU_0]>],
129 [6, 1], // Latency = 3, Repeat rate = 1
131 InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
132 InstrStage<1, [E500mc_LSU_0]>],
133 [6, 1], // Latency = 3
135 InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
136 InstrStage<1, [E500mc_LSU_0]>],
137 [6, 1], // Latency = 3
139 InstrItinData<IIC_LdStLoad, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
140 InstrStage<1, [E500mc_LSU_0]>],
141 [6, 1], // Latency = 3
143 InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
144 InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
145 InstrStage<1, [E500mc_LSU_0]>],
146 [6, 1], // Latency = 3
148 2>, // 2 micro-ops
149 InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
150 InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
151 InstrStage<1, [E500mc_LSU_0]>],
152 [6, 1], // Latency = 3
154 2>, // 2 micro-ops
155 InstrItinData<IIC_LdStStore, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
156 InstrStage<1, [E500mc_LSU_0]>],
157 [6, 1], // Latency = 3
159 InstrItinData<IIC_LdStSTU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
160 InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
161 InstrStage<1, [E500mc_LSU_0]>],
162 [6, 1], // Latency = 3
164 2>, // 2 micro-ops
165 InstrItinData<IIC_LdStSTUX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
166 InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
167 InstrStage<1, [E500mc_LSU_0]>],
168 [6, 1], // Latency = 3
170 2>, // 2 micro-ops
171 InstrItinData<IIC_LdStICBI, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
172 InstrStage<1, [E500mc_LSU_0]>],
173 [6, 1], // Latency = 3
175 InstrItinData<IIC_LdStSTFD, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
176 InstrStage<1, [E500mc_LSU_0]>],
177 [6, 1, 1], // Latency = 3
180 InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
181 InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
182 InstrStage<1, [E500mc_LSU_0]>],
183 [6, 1, 1], // Latency = 3
186 2>, // 2 micro-ops
187 InstrItinData<IIC_LdStLFD, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
188 InstrStage<1, [E500mc_LSU_0]>],
189 [7, 1, 1], // Latency = 4
192 InstrItinData<IIC_LdStLFDU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
193 InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
194 InstrStage<1, [E500mc_LSU_0]>],
195 [7, 1, 1], // Latency = 4
198 2>, // 2 micro-ops
199 InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
200 InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
201 InstrStage<1, [E500mc_LSU_0]>],
202 [7, 1, 1], // Latency = 4
205 2>, // 2 micro-ops
206 InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
207 InstrStage<1, [E500mc_LSU_0]>],
208 [6, 1], // Latency = 3
210 InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
211 InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
212 InstrStage<1, [E500mc_LSU_0]>],
213 [6, 1], // Latency = 3
215 InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
216 InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
217 InstrStage<1, [E500mc_LSU_0]>],
218 [6, 1], // Latency = 3
220 InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
221 InstrStage<1, [E500mc_LSU_0]>],
222 [7, 1], // Latency = r+3
224 InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
226 [6, 1, 1], // Latency = 3, Repeat rate = 3
229 InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
230 InstrStage<1, [E500mc_LSU_0]>],
231 [6, 1], // Latency = 3
233 InstrItinData<IIC_LdStSync, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
234 InstrStage<1, [E500mc_LSU_0]>]>,
235 InstrItinData<IIC_SprMFSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
237 [7, 1],
239 InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
241 [5, 1], // Latency = 2, Repeat rate = 4
243 InstrItinData<IIC_SprMTSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
244 InstrStage<1, [E500mc_SFX0]>],
245 [5, 1],
247 InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
248 InstrStage<1, [E500mc_LSU_0], 0>]>,
249 InstrItinData<IIC_SprMFCR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
251 [8, 1],
253 InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
255 [8, 1],
257 InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
259 [7, 1], // Latency = 4, Repeat rate = 4
261 InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
263 [7, 1], // Latency = 4, Repeat rate = 4
265 InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
266 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
267 [4, 1], // Latency = 1, Repeat rate = 1
269 InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
270 InstrStage<1, [E500mc_SFX0]>],
271 [4, 1], // Latency = 1, Repeat rate = 1
273 InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
275 [7, 1], // Latency = 4, Repeat rate = 4
277 InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
278 InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
279 [4, 1], // Latency = 1, Repeat rate = 1
281 InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
282 InstrStage<1, [E500mc_SFX0]>],
283 [4, 1],
285 InstrItinData<IIC_FPGeneral, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
287 [11, 1, 1], // Latency = 8, Repeat rate = 2
290 InstrItinData<IIC_FPAddSub, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
292 [13, 1, 1], // Latency = 10, Repeat rate = 4
295 InstrItinData<IIC_FPCompare, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
297 [11, 1, 1], // Latency = 8, Repeat rate = 2
300 InstrItinData<IIC_FPDivD, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
302 [71, 1, 1], // Latency = 68, Repeat rate = 68
305 InstrItinData<IIC_FPDivS, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
307 [41, 1, 1], // Latency = 38, Repeat rate = 38
310 InstrItinData<IIC_FPFused, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
312 [13, 1, 1, 1], // Latency = 10, Repeat rate = 4
316 InstrItinData<IIC_FPRes, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
318 [41, 1], // Latency = 38, Repeat rate = 38
322 // ===---------------------------------------------------------------------===//
326 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.