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1 //===-- PPCScheduleE500.td - e500 Scheduling Defs ------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the itinerary class data for the Freescale e500 32-bit
13 // Freescale Document Number E500MCRM, Rev. 1, 03/2012.
15 //===----------------------------------------------------------------------===//
21 def E500_DIS0 : FuncUnit; // Dispatch stage - insn 1
22 def E500_DIS1 : FuncUnit; // Dispatch stage - insn 2
28 def E500_SU1 : FuncUnit; // Simple unit 1
41 InstrItinData<IIC_IntSimple, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
42 InstrStage<1, [E500_SU0, E500_SU1]>],
43 [4, 1, 1], // Latency = 1
46 InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
47 InstrStage<1, [E500_SU0, E500_SU1]>],
48 [4, 1, 1], // Latency = 1
51 InstrItinData<IIC_IntISEL, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
52 InstrStage<1, [E500_SU0, E500_SU1]>],
53 [4, 1, 1, 1], // Latency = 1
57 InstrItinData<IIC_IntCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
58 InstrStage<1, [E500_SU0, E500_SU1]>],
59 [5, 1, 1], // Latency = 1 or 2
62 InstrItinData<IIC_IntDivW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
63 InstrStage<1, [E500_MU], 0>,
65 [17, 1, 1], // Latency=4..35, Repeat= 4..35
68 InstrItinData<IIC_IntMulHW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
70 [7, 1, 1], // Latency = 4, Repeat rate = 1
73 InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
75 [7, 1, 1], // Latency = 4, Repeat rate = 1
78 InstrItinData<IIC_IntMulLI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
80 [7, 1, 1], // Latency = 4, Repeat rate = 1
83 InstrItinData<IIC_IntRotate, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
84 InstrStage<1, [E500_SU0, E500_SU1]>],
85 [4, 1, 1], // Latency = 1
88 InstrItinData<IIC_IntShift, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
89 InstrStage<1, [E500_SU0, E500_SU1]>],
90 [4, 1, 1], // Latency = 1
93 InstrItinData<IIC_IntTrapW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
95 [5, 1], // Latency = 2, Repeat rate = 2
97 InstrItinData<IIC_BrB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
98 InstrStage<1, [E500_BU]>],
99 [4, 1], // Latency = 1
101 InstrItinData<IIC_BrCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
102 InstrStage<1, [E500_BU]>],
103 [4, 1, 1], // Latency = 1
106 InstrItinData<IIC_BrMCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
107 InstrStage<1, [E500_BU]>],
108 [4, 1], // Latency = 1
110 InstrItinData<IIC_BrMCRX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
111 InstrStage<1, [E500_SU0, E500_SU1]>],
112 [4, 1, 1], // Latency = 1
114 InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
115 InstrStage<1, [E500_LSU_0]>],
116 [6, 1], // Latency = 3, Repeat rate = 1
118 InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
119 InstrStage<1, [E500_LSU_0]>],
120 [6, 1], // Latency = 3
122 InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
123 InstrStage<1, [E500_LSU_0]>],
124 [6, 1], // Latency = 3
126 InstrItinData<IIC_LdStLoad, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
127 InstrStage<1, [E500_LSU_0]>],
128 [6, 1], // Latency = 3
130 InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
131 InstrStage<1, [E500_SU0, E500_SU1], 0>,
132 InstrStage<1, [E500_LSU_0]>],
133 [6, 1], // Latency = 3
135 2>, // 2 micro-ops
136 InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
137 InstrStage<1, [E500_SU0, E500_SU1], 0>,
138 InstrStage<1, [E500_LSU_0]>],
139 [6, 1], // Latency = 3
141 2>, // 2 micro-ops
142 InstrItinData<IIC_LdStStore, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
143 InstrStage<1, [E500_LSU_0]>],
144 [6, 1], // Latency = 3
146 InstrItinData<IIC_LdStSTU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
147 InstrStage<1, [E500_SU0, E500_SU1], 0>,
148 InstrStage<1, [E500_LSU_0]>],
149 [6, 1], // Latency = 3
151 2>, // 2 micro-ops
152 InstrItinData<IIC_LdStSTUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
153 InstrStage<1, [E500_SU0, E500_SU1], 0>,
154 InstrStage<1, [E500_LSU_0]>],
155 [6, 1], // Latency = 3
157 2>, // 2 micro-ops
158 InstrItinData<IIC_LdStICBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
159 InstrStage<1, [E500_LSU_0]>],
160 [6, 1], // Latency = 3
162 InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
163 InstrStage<1, [E500_LSU_0]>],
164 [6, 1], // Latency = 3
166 InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
167 InstrStage<1, [E500_SU0, E500_SU1], 0>,
168 InstrStage<1, [E500_LSU_0]>],
169 [6, 1], // Latency = 3
171 InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
172 InstrStage<1, [E500_SU0, E500_SU1], 0>,
173 InstrStage<1, [E500_LSU_0]>],
174 [6, 1], // Latency = 3
176 InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
177 InstrStage<1, [E500_LSU_0]>],
178 [7, 1], // Latency = r+3
180 InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
182 [6, 1, 1], // Latency = 3, Repeat rate = 3
185 InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
186 InstrStage<1, [E500_LSU_0]>],
187 [6, 1], // Latency = 3
189 InstrItinData<IIC_LdStSync, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
190 InstrStage<1, [E500_LSU_0]>]>,
191 InstrItinData<IIC_SprMFSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
193 [7, 1],
195 InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
197 [5, 1], // Latency = 2, Repeat rate = 4
199 InstrItinData<IIC_SprMTSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
200 InstrStage<1, [E500_SU0]>],
201 [5, 1],
203 InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
204 InstrStage<1, [E500_LSU_0], 0>]>,
205 InstrItinData<IIC_SprMFCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
207 [8, 1],
209 InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
211 [8, 1],
213 InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
215 [7, 1], // Latency = 4, Repeat rate = 4
217 InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
219 [7, 1], // Latency = 4, Repeat rate = 4
221 InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
222 InstrStage<1, [E500_SU0, E500_SU1]>],
223 [4, 1], // Latency = 1, Repeat rate = 1
225 InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
226 InstrStage<1, [E500_SU0]>],
227 [4, 1], // Latency = 1, Repeat rate = 1
229 InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
231 [7, 1], // Latency = 4, Repeat rate = 4
233 InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
234 InstrStage<1, [E500_SU0, E500_SU1]>],
235 [4, 1], // Latency = 1, Repeat rate = 1
237 InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
238 InstrStage<1, [E500_SU0]>],
239 [4, 1],
241 InstrItinData<IIC_FPDGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
243 [9, 1, 1], // Latency = 6, Repeat rate = 1
245 InstrItinData<IIC_FPSGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
247 [7, 1, 1], // Latency = 4, Repeat rate = 1
249 InstrItinData<IIC_FPDivD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
251 [35, 1, 1], // Latency = 32, Repeat rate = 32
253 InstrItinData<IIC_FPDivS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
255 [32, 1, 1], // Latency = 29, Repeat rate = 29
257 InstrItinData<IIC_VecGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
258 InstrStage<1, [E500_SU0]>],
259 [4, 1, 1], // Latency = 1, Repeat rate = 1
261 InstrItinData<IIC_VecComplex, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
263 [7, 1, 1], // Latency = 4, Repeat rate = 1
267 // ===---------------------------------------------------------------------===//
271 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.