Lines Matching defs:ShiftBits

983     // rlwinm rA, rA, ShiftBits, 0, 31.
1028     unsigned ShiftBits = getEncodingValue(DestReg)*4;
1029     // rlwinm r11, r11, 32-ShiftBits, 0, 31.
1031              .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
1142     // rlwinm rA, rA, ShiftBits, 0, 0.
1190   unsigned ShiftBits = getEncodingValue(DestReg);
1191   // rlwimi r11, r10, 32-ShiftBits, ..., ...
1195       .addImm(ShiftBits ? 32 - ShiftBits : 0)
1196       .addImm(ShiftBits)
1197       .addImm(ShiftBits);