Lines Matching defs:MF
169 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
185 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
186 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
187 if (MF->getFunction().getCallingConv() == CallingConv::AnyReg) {
212 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2) &&
216 if (MF->getFunction().getCallingConv() == CallingConv::Cold) {
278 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
280 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
354 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
356 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
357 const PPCFrameLowering *TFI = getFrameLowering(MF);
390 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
391 if (!TM.isPPC64() || FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm())
405 if (TFI->needsFP(MF))
409 if (hasBasePointer(MF)) {
442 bool PPCRegisterInfo::isAsmClobberable(const MachineFunction &MF,
454 bool PPCRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const {
455 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
457 const MachineFrameInfo &MFI = MF.getFrameInfo();
460 LLVM_DEBUG(dbgs() << "requiresFrameIndexScavenging for " << MF.getName()
529 const MachineFunction &MF) const {
530 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
539 const MachineFunction &MF) const {
541 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
542 const MachineFrameInfo &MFI = MF.getFrameInfo();
551 return (getReservedRegs(MF).test(PhysReg));
564 const MachineFunction &MF,
567 const MachineRegisterInfo *MRI = &MF.getRegInfo();
577 VirtReg, Order, Hints, MF, VRM, Matrix);
582 if (MF.getSubtarget<PPCSubtarget>().isISAFuture())
635 MachineFunction &MF) const {
636 const PPCFrameLowering *TFI = getFrameLowering(MF);
647 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
656 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
666 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
680 const MachineFunction &MF) const {
681 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
683 TargetRegisterInfo::getLargestLegalSuperClass(RC, MF);
740 MachineFunction &MF = *MBB.getParent();
742 MachineFrameInfo &MFI = MF.getFrameInfo();
743 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
759 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
800 MachineFunction &MF = *MBB.getParent();
802 MachineFrameInfo &MFI = MF.getFrameInfo();
803 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
813 const PPCFrameLowering *TFI = getFrameLowering(MF);
848 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
856 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
865 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
873 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
888 MachineFunction &MF = *MBB.getParent();
889 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
930 MachineFunction &MF = *MBB.getParent();
932 MachineFrameInfo &MFI = MF.getFrameInfo();
933 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
960 MachineFunction &MF = *MBB.getParent();
961 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
969 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
981 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
1005 MachineFunction &MF = *MBB.getParent();
1006 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1014 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
1026 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
1048 MachineFunction &MF = *MBB.getParent();
1049 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1058 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
1140 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
1167 MachineFunction &MF = *MBB.getParent();
1168 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1176 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
1186 Register RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
1283 MachineFunction &MF = *MBB.getParent();
1284 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1317 MachineFunction &MF = *MBB.getParent();
1318 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1360 MachineFunction &MF = *MBB.getParent();
1361 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1395 MachineFunction &MF = *MBB.getParent();
1396 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1404 Register VSRpReg0 = MF.getRegInfo().createVirtualRegister(RC);
1405 Register VSRpReg1 = MF.getRegInfo().createVirtualRegister(RC);
1429 MachineFunction &MF = *MBB.getParent();
1430 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1438 Register VSRpReg0 = MF.getRegInfo().createVirtualRegister(RC);
1439 Register VSRpReg1 = MF.getRegInfo().createVirtualRegister(RC);
1461 MachineFunction &MF = *MBB.getParent();
1462 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1488 MachineFunction &MF = *MBB.getParent();
1489 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1509 bool PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
1520 FrameIdx = MF.getInfo<PPCFunctionInfo>()->getCRSpillFrameIndex();
1590 MachineFunction &MF = *MBB.getParent();
1591 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1595 MachineFrameInfo &MFI = MF.getFrameInfo();
1605 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1672 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false);
1689 if (!MF.getFunction().hasFnAttribute(Attribute::Naked)) {
1690 if (!(hasBasePointer(MF) && FrameIndex < 0))
1747 VSReg = MF.getRegInfo().createVirtualRegister(&PPC::VSFRCRegClass);
1751 SRegHi = MF.getRegInfo().createVirtualRegister(RC);
1752 SReg = MF.getRegInfo().createVirtualRegister(RC);
1804 Register NewReg = MF.getRegInfo().createVirtualRegister(&PPC::G8RCRegClass);
1815 Register PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1816 const PPCFrameLowering *TFI = getFrameLowering(MF);
1819 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
1821 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
1824 Register PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
1825 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1826 if (!hasBasePointer(MF))
1827 return getFrameRegister(MF);
1838 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
1847 return hasStackRealignment(MF);
1877 MachineFunction &MF = *MBB.getParent();
1878 const PPCFrameLowering *TFI = getFrameLowering(MF);
1879 unsigned StackEst = TFI->determineFrameLayout(MF, true);
1894 return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset);
1909 const MachineFunction &MF = *MBB->getParent();
1910 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1914 const TargetRegisterClass *RC = getPointerRegClass(MF);
1916 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
1939 MachineFunction &MF = *MBB.getParent();
1940 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1943 MachineRegisterInfo &MRI = MF.getRegInfo();
1945 TII.getRegClass(MCID, FIOperandNum, this, MF));