Lines Matching full:ra
42 // load rt, ra, rx
102 // [addi rt,ra,si - lxvd2x xt,ra,rb] etc. in checkOpConstraints()
104 // lxvd2x(ra) cannot be zero in checkOpConstraints()
105 const MachineOperand &RA = SecondMI.getOperand(1); in checkOpConstraints() local
106 if (!RA.isReg()) in checkOpConstraints()
109 return RA.getReg().isVirtual() || in checkOpConstraints()
110 (RA.getReg() != PPC::ZERO && RA.getReg() != PPC::ZERO8); in checkOpConstraints()
112 // [addis rt,ra,si - ld rt,ds(ra)] etc. in checkOpConstraints()
120 // addis(rt) = ld(ra) = ld(rt) in checkOpConstraints()
155 // rldicl rx, ra, 1, 0 - xor in checkOpConstraints()
159 // rldicr rx, ra, 1, 63 - xor in checkOpConstraints()
203 // addis rx,ra,si - addi rt,rx,SI, SI >= 0 in checkOpConstraints()
205 const MachineOperand &RA = FirstMI.getOperand(1); in checkOpConstraints() local
207 if (!SI.isImm() || !RA.isReg()) in checkOpConstraints()
209 if (RA.getReg() == PPC::ZERO || RA.getReg() == PPC::ZERO8) in checkOpConstraints()
214 // addi rx,ra,si - addis rt,rx,SI, ra > 0, SI >= 2 in checkOpConstraints()
216 const MachineOperand &RA = FirstMI.getOperand(1); in checkOpConstraints() local
218 if (!SI.isImm() || !RA.isReg()) in checkOpConstraints()
220 if (RA.getReg() == PPC::ZERO || RA.getReg() == PPC::ZERO8) in checkOpConstraints()