Lines Matching defs:isPPC64
179 bool isPPC64 = Subtarget.isPPC64();
180 setMinStackArgumentAlignment(isPPC64 ? Align(8) : Align(4));
262 if (isPPC64 || Subtarget.hasFPCVT()) {
265 isPPC64 ? MVT::i64 : MVT::i32);
268 isPPC64 ? MVT::i64 : MVT::i32);
272 isPPC64 ? MVT::i64 : MVT::i32);
275 isPPC64 ? MVT::i64 : MVT::i32);
279 isPPC64 ? MVT::i64 : MVT::i32);
282 isPPC64 ? MVT::i64 : MVT::i32);
286 isPPC64 ? MVT::i64 : MVT::i32);
289 isPPC64 ? MVT::i64 : MVT::i32);
480 (Subtarget.hasP9Vector() && Subtarget.isPPC64()) ? Custom : Expand);
560 if (Subtarget.hasDirectMove() && isPPC64) {
705 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) {
1007 if (Subtarget.hasDirectMove() && isPPC64) {
1307 setOperationAction(ISD::SELECT_CC, MVT::i64, isPPC64 ? Custom : Expand);
1360 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
1362 if (!isPPC64) {
1382 else if (isPPC64)
1387 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
1435 setLibcallName(RTLIB::MEMCPY, isPPC64 ? "___memmove64" : "___memmove");
1436 setLibcallName(RTLIB::MEMMOVE, isPPC64 ? "___memmove64" : "___memmove");
1437 setLibcallName(RTLIB::MEMSET, isPPC64 ? "___memset64" : "___memset");
1438 setLibcallName(RTLIB::BZERO, isPPC64 ? "___bzero64" : "___bzero");
1632 Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4);
1652 if (!Subtarget.isPPC64() || !Subtarget.hasVSX())
2867 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2974 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
3178 const bool Is64Bit = Subtarget.isPPC64();
3242 if (Subtarget.isPPC64() || Subtarget.isAIXABI())
3249 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
3266 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
3419 bool Is64Bit = Subtarget.isPPC64();
3562 bool is64bit = Subtarget.isPPC64();
3811 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
3902 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
3983 bool isPPC64 = (PtrVT == MVT::i64);
3992 // TrampSize == (isPPC64 ? 48 : 40);
3993 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
3994 isPPC64 ? MVT::i64 : MVT::i32);
4017 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) {
5222 bool isPPC64 = Subtarget.isPPC64();
5223 int SlotSize = isPPC64 ? 8 : 4;
5227 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
5238 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
5244 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
5261 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
5288 SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64,
5295 if (isPPC64)
5305 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
5657 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
5658 const Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4);
5707 const bool IsPPC64 = Subtarget.isPPC64();
5883 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64())
5963 if (Subtarget.isPPC64())
6848 const bool IsPPC64 = Subtarget.isPPC64();
7204 const bool IsPPC64 = Subtarget.isPPC64();
7516 const bool IsPPC64 = Subtarget.isPPC64();
7780 const MVT PtrVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
7911 bool isPPC64 = Subtarget.isPPC64();
7912 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
7932 bool isPPC64 = Subtarget.isPPC64();
7945 RASI = MF.getFrameInfo().CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
7955 bool isPPC64 = Subtarget.isPPC64();
7968 FPSI = MF.getFrameInfo().CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
8001 bool isPPC64 = Subtarget.isPPC64();
8004 int FI = MF.getFrameInfo().CreateFixedObject(isPPC64 ? 8 : 4, 0, false);
8345 DestTy = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
8518 if (Subtarget.hasDirectMove() && Subtarget.isPPC64())
8810 Subtarget.isPPC64() && Subtarget.hasFPCVT())
8991 assert(Subtarget.isPPC64() &&
9341 if (!Subtarget.isPPC64() || (Op0.getOpcode() != ISD::BUILD_PAIR) ||
9588 if (Subtarget.hasVSX() && Subtarget.isPPC64() &&
10449 bool isPPC64 = Subtarget.isPPC64();
10536 if (isPPC64 && (V1HasXXSWAPD || V2HasXXSWAPD)) {
10869 if (Subtarget.isPPC64())
10874 assert(Subtarget.isPPC64() && "rldimi is only available in 64-bit!");
11186 unsigned Opcode = Subtarget.isPPC64() ? PPC::CFENCE8 : PPC::CFENCE;
11187 EVT FTy = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
11203 if (!Subtarget.isPPC64())
11389 if (Subtarget.isPPC64()) {
11507 if ((VT == MVT::v2i64 || VT == MVT::v2f64) && !Subtarget.isPPC64())
11941 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64())
12240 bool is64bit = Subtarget.isPPC64();
12507 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
12509 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
12512 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
12535 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
12538 if (Subtarget.isPPC64()) {
12698 const bool isPPC64 = Subtarget.isPPC64();
12739 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
12740 Register FinalStackPtr = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
12741 Register FramePointer = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
12742 Register ActualNegSizeReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
12750 isPPC64 ? PPC::PREPARE_PROBED_ALLOCA_64 : PPC::PREPARE_PROBED_ALLOCA_32;
12756 ProbeOpc = isPPC64 ? PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64
12765 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::ADD8 : PPC::ADD4),
12773 Register ScratchReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
12775 Register TempReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
12776 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::LIS8 : PPC::LIS), TempReg)
12778 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::ORI8 : PPC::ORI),
12783 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::LI8 : PPC::LI), ScratchReg)
12788 Register Div = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
12789 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::DIVD : PPC::DIVW), Div)
12792 Register Mul = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
12793 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::MULLD : PPC::MULLW), Mul)
12796 Register NegMod = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
12797 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::SUBF8 : PPC::SUBF), NegMod)
12800 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::STDUX : PPC::STWUX), SPReg)
12809 BuildMI(TestMBB, DL, TII->get(isPPC64 ? PPC::CMPD : PPC::CMPW), CmpResult)
12823 BuildMI(BlockMBB, DL, TII->get(isPPC64 ? PPC::STDUX : PPC::STWUX), SPReg)
12834 MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
12836 TII->get(isPPC64 ? PPC::DYNAREAOFFSET8 : PPC::DYNAREAOFFSET),
12840 BuildMI(TailMBB, DL, TII->get(isPPC64 ? PPC::ADD8 : PPC::ADD4), DstReg)
13253 bool is64bit = Subtarget.isPPC64();
14370 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64())))
15376 (Op1VT == MVT::i32 || (Op1VT == MVT::i64 && Subtarget.isPPC64()) ||
15879 (Subtarget.hasLDBRX() && Subtarget.isPPC64() && Op1VT == MVT::i64))) {
15914 if (Subtarget.isPPC64() && !DCI.isBeforeLegalize() &&
16326 Subtarget.isPPC64() && N->getValueType(0) == MVT::i64;
16577 if (VT == MVT::i64 && !Subtarget.isPPC64())
16809 if (VT == MVT::i64 && Subtarget.isPPC64())
16813 if (VT == MVT::i64 && Subtarget.isPPC64())
16909 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
17087 bool isPPC64 = Subtarget.isPPC64();
17099 isPPC64 ? MVT::i64 : MVT::i32);
17121 bool isPPC64 = PtrVT == MVT::i64;
17127 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
17129 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
17143 bool isPPC64 = Subtarget.isPPC64();
17145 bool is64Bit = isPPC64 && VT == LLT::scalar(64);
17151 .Case("r2", isPPC64 ? Register() : PPC::R2)
17370 if (Subtarget.isPPC64()) {
17409 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
17593 return Subtarget.isPPC64() ? PPC::X3 : PPC::R3;
17598 return Subtarget.isPPC64() ? PPC::X4 : PPC::R4;
17801 if (!Subtarget.isISA3_0() || !Subtarget.isPPC64() ||
17845 if (!Subtarget.isPPC64())
18465 Disp = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
18686 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
18742 Disp = FI ? DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
18763 return Subtarget.isPPC64() && Subtarget.hasQuadwordAtomics();