Lines Matching defs:ShiftElts

2281 bool PPC::isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
2299     ShiftElts = IsLE ? LittleEndianShifts[M0 & 0x3] : BigEndianShifts[M0 & 0x3];
2307     ShiftElts = IsLE ? LittleEndianShifts[M1 & 0x3] : BigEndianShifts[M1 & 0x3];
2315     ShiftElts = IsLE ? LittleEndianShifts[M2 & 0x3] : BigEndianShifts[M2 & 0x3];
2323     ShiftElts = IsLE ? LittleEndianShifts[M3 & 0x3] : BigEndianShifts[M3 & 0x3];
2332     ShiftElts = 0;
2356 bool PPC::isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
2376     ShiftElts = IsLE ? (4 - M0) % 4 : M0;
2391       ShiftElts = (8 - M0) % 8;
2397       ShiftElts = (4 - M0) % 4;
2406       ShiftElts = M0;
2411       ShiftElts = M0 - 4;
9835   unsigned ShiftElts = 0, InsertAtByte = 0;
9893         ShiftElts = 0;
9897         ShiftElts = IsLE ? LittleEndianShifts[CurrentElement & 0xF]
9916   if (ShiftElts) {
9918                               DAG.getConstant(ShiftElts, dl, MVT::i32));
9941   unsigned ShiftElts = 0, InsertAtByte = 0;
9984       ShiftElts = 0;
10003         ShiftElts = IsLE ? LittleEndianShifts[MaskOneElt & 0x7]
10023   if (ShiftElts) {
10024     // Double ShiftElts because we're left shifting on v16i8 type.
10026                               DAG.getConstant(2 * ShiftElts, dl, MVT::i32));
10167   unsigned ShiftElts, InsertAtByte;
10233       PPC::isXXINSERTWMask(SVOp, ShiftElts, InsertAtByte, Swap,
10241     if (ShiftElts) {
10243                                 DAG.getConstant(ShiftElts, dl, MVT::i32));
10269       PPC::isXXSLDWIShuffleMask(SVOp, ShiftElts, Swap, isLittleEndian)) {
10277                               DAG.getConstant(ShiftElts, dl, MVT::i32));
10282     PPC::isXXPERMDIShuffleMask(SVOp, ShiftElts, Swap, isLittleEndian)) {
10290                               DAG.getConstant(ShiftElts, dl, MVT::i32));