Lines Matching defs:PVT
12441 MVT PVT = getPointerTy(MF->getDataLayout());
12442 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
12485 const int64_t LabelOffset = 1 * PVT.getStoreSize();
12486 const int64_t TOCOffset = 3 * PVT.getStoreSize();
12487 const int64_t BPOffset = 4 * PVT.getStoreSize();
12490 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
12573 MVT PVT = getPointerTy(MF->getDataLayout());
12574 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
12578 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
12581 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
12582 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
12584 (PVT == MVT::i64)
12591 const int64_t LabelOffset = 1 * PVT.getStoreSize();
12592 const int64_t SPOffset = 2 * PVT.getStoreSize();
12593 const int64_t TOCOffset = 3 * PVT.getStoreSize();
12594 const int64_t BPOffset = 4 * PVT.getStoreSize();
12601 if (PVT == MVT::i64) {
12613 if (PVT == MVT::i64) {
12625 if (PVT == MVT::i64) {
12637 if (PVT == MVT::i64) {
12649 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
12659 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
12660 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));