Lines Matching defs:N0
10121 SDValue N0 = peekThroughBitcasts(Op.getOperand(0));
10129 DAG.getVectorShuffle(MVT::v16i8, dl, DAG.getBitcast(MVT::v16i8, N0),
10133 SDValue ArgVal = DAG.getBitcast(MVT::i128, N0);
16584 SDValue N0 = N->getOperand(0);
16590 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
17657 SDValue N0 = Op.getOperand(0);
17676 SDValue NegN0 = getNegatedExpression(N0, DAG, LegalOps, OptForSize,
17688 return DAG.getNode(Opc, Loc, VT, N0, NegN1, NegN2, Flags);
17695 return DAG.getNode(ISD::FMA, Loc, VT, N0, N1, NegN2, Flags);
17765 SDValue N0 = N->getOperand(0);
17767 EVT VT = N0.getValueType();
17790 return DAG.getNode(TargetOpcode, SDLoc(N), VT, N0, N1->getOperand(0));
17799 SDValue N0 = N->getOperand(0);
17802 N0.getOpcode() != ISD::SIGN_EXTEND ||
17803 N0.getOperand(0).getValueType() != MVT::i32 || CN1 == nullptr ||
17809 SDValue ExtsSrc = N0.getOperand(0);
17814 SDLoc DL(N0);
17821 return DCI.DAG.getNode(PPCISD::EXTSWSLI, DL, MVT::i64, N0->getOperand(0),
18122 SDValue N0 = N->getOperand(0);
18144 if (SDValue NegN0 = getCheaperNegatedExpression(N0, DAG, LegalOps, CodeSize))
18150 return DAG.getNode(invertFMAOpcode(Opc), Loc, VT, N0, NegN1, N2, Flags);