Lines Matching defs:LocVT

6842 static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
6944 const unsigned StoreSize = LocVT.getStoreSize();
6951 State.addLoc(CCValAssign::getReg(ValNo, ValVT, FReg, LocVT, LocInfo));
6973 FReg ? CCValAssign::getCustomMem(ValNo, ValVT, Offset, LocVT,
6975 : CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
6996 State.addLoc(CCValAssign::getReg(ValNo, ValVT, VReg, LocVT, LocInfo));
7003 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
7026 State.addLoc(CCValAssign::getReg(ValNo, ValVT, VReg, LocVT, LocInfo));
7035 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
7042 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
7052 CCValAssign::getCustomMem(ValNo, ValVT, Offset, LocVT, LocInfo));
7070 CCValAssign::getCustomMem(ValNo, ValVT, Offset, LocVT, LocInfo));
7115 MVT LocVT, const SDLoc &dl) {
7116 assert(ValVT.isScalarInteger() && LocVT.isScalarInteger());
7117 assert(ValVT.getFixedSizeInBits() < LocVT.getFixedSizeInBits());
7120 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue,
7123 ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue,
7224 MVT LocVT = VA.getLocVT();
7237 const unsigned LocSize = LocVT.getStoreSize();
7367 auto HandleRegLoc = [&, RegClass, LocVT](const MCPhysReg PhysReg,
7373 SDValue CopyFrom = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
7418 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
7420 (ValVT.getFixedSizeInBits() < LocVT.getFixedSizeInBits())) {
7422 truncateScalarIntegerArg(Flags, ValVT, DAG, ArgValue, LocVT, dl);
7647 const MVT LocVT = VA.getLocVT();
7731 LocVT.isInteger() &&
7737 if (Arg.getValueType().getStoreSize() == LocVT.getStoreSize())
7742 LocVT.getFixedSizeInBits())
7745 VA.getLocReg(), DAG.getZExtOrTrunc(ArgAsInt, dl, LocVT)));