Lines Matching defs:IsPPC64
5707 const bool IsPPC64 = Subtarget.isPPC64();
5709 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
5747 Ops.push_back(DAG.getRegister(IsPPC64 ? PPC::CTR8 : PPC::CTR, RegVT));
6848 const bool IsPPC64 = Subtarget.isPPC64();
6849 const unsigned PtrSize = IsPPC64 ? 8 : 4;
6852 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
6872 const ArrayRef<MCPhysReg> GPRs = IsPPC64 ? GPR_64 : GPR_32;
6925 assert(IsPPC64 && "PPC32 should have split i64 values.");
6948 State.AllocateStack(IsPPC64 ? 8 : StoreSize, Align(4));
7085 bool IsPPC64,
7088 assert((IsPPC64 || SVT != MVT::i64) &&
7097 return IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
7204 const bool IsPPC64 = Subtarget.isPPC64();
7205 const unsigned PtrByteSize = IsPPC64 ? 8 : 4;
7277 getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(),
7291 assert(!IsPPC64 &&
7365 IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
7416 getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(),
7457 const unsigned NumGPArgRegs = std::size(IsPPC64 ? GPR_64 : GPR_32);
7467 IsPPC64 ? MF.addLiveIn(GPR_64[GPRIndex], &PPC::G8RCRegClass)
7516 const bool IsPPC64 = Subtarget.isPPC64();
7518 const unsigned PtrByteSize = IsPPC64 ? 8 : 4;
7543 const SDValue StackPtr = IsPPC64 ? DAG.getRegister(PPC::X1, MVT::i64)
7705 assert(!IsPPC64 &&
7749 assert(Arg.getValueType() == MVT::f64 && CFlags.IsVarArg && !IsPPC64 &&