Lines Matching defs:SPReg
652 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
814 .addReg(SPReg);
828 .addReg(SPReg);
833 .addReg(SPReg);
838 .addReg(SPReg);
849 .addReg(SPReg);
867 .addReg(SPReg);
880 .addReg(SPReg);
896 .addReg(SPReg)
897 .addReg(SPReg);
933 .addReg(SPReg);
940 .addReg(SPReg)
945 .addReg(SPReg)
961 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
962 .addReg(SPReg, RegState::Kill)
963 .addReg(SPReg)
966 BuildMI(MBB, StackUpdateLoc, dl, StoreUpdtInst, SPReg)
967 .addReg(SPReg)
969 .addReg(SPReg);
972 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
973 .addReg(SPReg, RegState::Kill)
974 .addReg(SPReg)
986 .addReg(SPReg);
992 // The negated frame size is in ScratchReg, and the SPReg has been
993 // decremented by the frame size: SPReg = old SPReg + ScratchReg.
1004 .addReg(SPReg);
1078 // Since the SPReg has been decreased by FrameSize, add it back to each
1084 .addReg(SPReg);
1089 .addReg(SPReg);
1094 .addReg(SPReg);
1096 .addReg(SPReg)
1166 .addReg(SPReg)
1167 .addReg(SPReg);
1260 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1311 BuildMI(MBB, MBBI, DL, TII.get(isPPC64 ? PPC::STDU : PPC::STWU), SPReg)
1314 .addReg(SPReg);
1316 BuildMI(MBB, MBBI, DL, TII.get(isPPC64 ? PPC::STDUX : PPC::STWUX), SPReg)
1318 .addReg(SPReg)
1405 .addReg(SPReg)
1408 BuildMI(&MBB, DL, CopyInst, TempReg).addReg(SPReg).addReg(SPReg);
1450 .addReg(SPReg)
1455 .addReg(SPReg)
1462 .addReg(SPReg);
1473 BuildMI(*CurrentMBB, {MI}, DL, CopyInst, FPReg).addReg(SPReg).addReg(SPReg);
1494 // Restore using SPReg to calculate CFA.
1495 buildDefCFAReg(*CurrentMBB, {MI}, SPReg);
1528 // Restore using SPReg to calculate CFA.
1529 buildDefCFAReg(*ExitMBB, ExitMBB->begin(), SPReg);
1571 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1671 unsigned RBReg = SPReg;
1738 BuildMI(MBB, StackUpdateLoc, dl, AddImmInst, SPReg)
1739 .addReg(SPReg)
1764 .addReg(SPReg);
1780 .addReg(SPReg);
1791 if (MustSaveLR && RBReg == SPReg && isInt<16>(LROffset+SPAdd)) {
1799 assert(RBReg == SPReg && "Should be using SP as a base register");
1808 if (HasRedZone || RBReg == SPReg)
1811 .addReg(SPReg);
1830 if (RBReg != SPReg || SPAdd != 0) {
1834 BuildMI(MBB, MBBI, dl, OrInst, SPReg)
1838 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1852 .addReg(SPReg);
1874 .addReg(SPReg);
1890 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1891 .addReg(SPReg).addImm(CallerAllocatedAmt);
1899 .addReg(SPReg)