Lines Matching defs:Ws
2667 SDValue Ws;
2683 Ws = Op->getOperand(0);
2685 Ws = Op->getOperand(1);
2689 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Ws, Wt);
2713 SDValue Ws;
2729 Ws = Op->getOperand(0);
2731 Ws = Op->getOperand(1);
2735 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Wt, Ws);
2760 SDValue Ws;
2776 Ws = Op->getOperand(0);
2778 Ws = Op->getOperand(1);
2782 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Ws, Wt);
2808 SDValue Ws;
2824 Ws = Op->getOperand(0);
2827 Ws = Op->getOperand(1);
2831 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Ws, Wt);
2855 SDValue Ws;
2868 Ws = Op->getOperand(0);
2870 Ws = Op->getOperand(1);
2874 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Ws, Wt);
2898 SDValue Ws;
2911 Ws = Op->getOperand(0);
2913 Ws = Op->getOperand(1);
2917 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Ws, Wt);
3169 Register Ws = MI.getOperand(1).getReg();
3173 unsigned Wt = Ws;
3179 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
3188 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
3214 Register Ws = MI.getOperand(1).getReg();
3219 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
3223 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
3508 Register Ws = MI.getOperand(0).getReg();
3523 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0);
3713 // / FGR64Opnd:$Fd and MSA128F16:$Ws to the same physical register
3763 Register Ws = MI.getOperand(1).getReg();
3776 BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_W), Wtemp).addReg(Ws);