Lines Matching defs:ResTy
410 EVT ResTy = Op->getValueType(0);
417 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1),
1360 EVT ResTy = Op->getValueType(0);
1363 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1504 EVT ResTy = Op->getValueType(0);
1507 MVT ResEltTy = ResTy == MVT::v2i64 ? MVT::i64 : MVT::i32;
1510 SDValue SplatVec = getBuildVectorSplat(ResTy, ConstValue, BigEndian, DAG);
1512 return DAG.getNode(ISD::AND, DL, ResTy, Vec, SplatVec);
1516 EVT ResTy = Op->getValueType(0);
1518 SDValue One = DAG.getConstant(1, DL, ResTy);
1519 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, truncateVecElts(Op, DAG));
1521 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1522 DAG.getNOT(DL, Bit, ResTy));
1527 EVT ResTy = Op->getValueType(0);
1528 APInt BitImm = APInt(ResTy.getScalarSizeInBits(), 1)
1530 SDValue BitMask = DAG.getConstant(~BitImm, DL, ResTy);
1532 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1876 EVT ResTy = Op->getValueType(0);
1877 SmallVector<SDValue, 16> Ops(ResTy.getVectorNumElements(),
1880 // If ResTy is v2i64 then the type legalizer will break this node down into
1882 return DAG.getBuildVector(ResTy, DL, Ops);
1887 EVT ResTy = Op->getValueType(0);
1889 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1890 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1986 EVT ResTy = Op->getValueType(0);
1987 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1988 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1995 EVT ResTy = Op->getValueType(0);
1996 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1997 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2070 EVT ResTy = Op->getValueType(0);
2071 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
2072 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2294 EVT ResTy = Op->getValueType(0);
2304 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(),
2407 EVT ResTy = Op->getValueType(0);
2414 if (ResTy.isInteger()) {
2417 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2457 EVT ResTy = Op->getValueType(0);
2463 if (!Subtarget.hasMSA() || !ResTy.is128BitVector())
2477 if (ResTy.isInteger() && !HasAnyUndefs)
2503 if (ViaVecTy != ResTy)
2504 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
2513 EVT ResTy = Node->getValueType(0);
2515 assert(ResTy.isVector());
2517 unsigned NumElts = ResTy.getVectorNumElements();
2518 SDValue Vector = DAG.getUNDEF(ResTy);
2520 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2548 static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
2593 return DAG.getNode(MipsISD::SHF, DL, ResTy,
2629 static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy,
2661 static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
2689 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Ws, Wt);
2707 static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
2735 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Wt, Ws);
2754 static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
2782 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Ws, Wt);
2801 static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
2831 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Ws, Wt);
2849 static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
2874 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Ws, Wt);
2892 static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
2917 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Ws, Wt);
2928 static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
2934 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2939 int ResTyNumElts = ResTy.getVectorNumElements();
2973 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0);
2981 EVT ResTy = Op->getValueType(0);
2983 if (!ResTy.is128BitVector())
2986 int ResTyNumElts = ResTy.getVectorNumElements();
2994 if (isVECTOR_SHUFFLE_SPLATI(Op, ResTy, Indices, DAG))
2995 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2997 if ((Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG)))
2999 if ((Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG)))
3001 if ((Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG)))
3003 if ((Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG)))
3005 if ((Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG)))
3007 if ((Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG)))
3009 if ((Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG)))
3011 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);