Lines Matching +full:hi +full:- +full:fi
1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
38 #define DEBUG_TYPE "mips-isel"
42 if (Subtarget->inMips16Mode())
79 uint64_t RegNum = RegIdx->getAsZExtVal();
106 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
107 E = MRI->use_end(); U != E;) {
114 if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
119 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
131 if (!Subtarget->isABI_O32()) { // N32, N64
133 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::OR64))
141 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::OR))
146 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::ADDiu))
149 .addImm(-8);
156 MF.getInfo<MipsFunctionInfo>()->initGlobalBaseReg(MF);
171 if (!Subtarget->useOddSPReg()) {
178 if (Subtarget->isABI_FPXX() && !Subtarget->hasMTHC1())
184 MI.getOperand(0).getGlobal()->getGlobalIdentifier() == "_mcount")
191 MI.getOperand(2).getMCSymbol()->getName() == "_mcount")
196 MI.getOperand(3).getMCSymbol()->getName() == "_mcount")
207 SDValue InGlue = Node->getOperand(2);
209 SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
216 CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Ops);
234 SDValue CstOne = CurDAG->getTargetConstant(1, DL, MVT::i32);
236 SDValue OuFlag = CurDAG->getTargetConstant(20, DL, MVT::i32);
238 SDNode *DSPCtrlField = CurDAG->getMachineNode(Mips::RDDSP, DL, MVT::i32,
241 SDNode *Carry = CurDAG->getMachineNode(
245 CurDAG->getTargetConstant(6, DL, MVT::i32), CstOne,
247 SDNode *DSPCFWithCarry = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, Ops);
254 SDValue Zero = CurDAG->getRegister(Mips::ZERO, MVT::i32);
258 CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps);
260 SDNode *WrDSP = CurDAG->getMachineNode(Mips::WRDSP, DL, MVT::Glue,
264 CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Operands);
273 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
274 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy);
284 if (CurDAG->isBaseWithConstantOffset(Addr)) {
286 if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) {
289 // If the first operand is a FI, get the TargetFI Node
292 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
295 // If base is a FI, additional offset calculation is done in
298 if (!isAligned(Alignment, CN->getZExtValue()))
302 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
314 // if Address is FI, get the TargetFrameIndex.
331 // Addresses of the form FI+const or FI|const
339 // lui $2, %hi($CPI1_0)
343 // lui $2, %hi($CPI1_0)
365 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType());
386 /// Used on microMIPS LWC2, LDC2, SWC2 and SDC2 instructions (11-bit offset)
398 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
446 unsigned CnstOff = CN->getZExtValue();
513 if (!Subtarget->hasMSA())
525 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
526 MinSizeInBits, !Subtarget->isLittle()))
539 // * The splat value fits in an integer with the specified signed-ness and
543 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
544 // sometimes a shuffle in big-endian mode.
547 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
554 EVT EltTy = N->getValueType(0).getVectorElementType();
556 if (N->getOpcode() == ISD::BITCAST)
557 N = N->getOperand(0);
564 Imm = CurDAG->getTargetConstant(ImmValue, SDLoc(N), EltTy);
626 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
627 // sometimes a shuffle in big-endian mode.
630 EVT EltTy = N->getValueType(0).getVectorElementType();
632 if (N->getOpcode() == ISD::BITCAST)
633 N = N->getOperand(0);
639 if (Log2 != -1) {
640 Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
649 // of left-most bits set (e.g. 0b11...1100...00).
654 // * The splat value is a consecutive sequence of left-most bits.
657 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
658 // sometimes a shuffle in big-endian mode.
661 EVT EltTy = N->getValueType(0).getVectorElementType();
663 if (N->getOpcode() == ISD::BITCAST)
664 N = N->getOperand(0);
673 Imm = CurDAG->getTargetConstant(ImmValue.popcount() - 1, SDLoc(N), EltTy);
682 // of right-most bits set (e.g. 0b00...0011...11).
687 // * The splat value is a consecutive sequence of right-most bits.
690 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
691 // sometimes a shuffle in big-endian mode.
694 EVT EltTy = N->getValueType(0).getVectorElementType();
696 if (N->getOpcode() == ISD::BITCAST)
697 N = N->getOperand(0);
704 Imm = CurDAG->getTargetConstant(ImmValue.popcount() - 1, SDLoc(N), EltTy);
715 EVT EltTy = N->getValueType(0).getVectorElementType();
717 if (N->getOpcode() == ISD::BITCAST)
718 N = N->getOperand(0);
724 if (Log2 != -1) {
725 Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
736 EVT EltTy = N->getValueType(0).getVectorElementType();
738 if (N->getOpcode() == ISD::BITCAST)
739 N = N->getOperand(0);
746 unsigned Opcode = Node->getOpcode();
750 // Instruction Selection not handled by the auto-generated
758 MVT VT = Subtarget->isGP64bit() ? MVT::i64 : MVT::i32;
759 SDValue cond = Node->getOperand(0);
760 SDValue Hi1 = Node->getOperand(1);
761 SDValue Lo1 = Node->getOperand(2);
762 SDValue Hi2 = Node->getOperand(3);
763 SDValue Lo2 = Node->getOperand(4);
767 ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->isGP64bit()
781 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
782 if (Subtarget->isGP64bit()) {
783 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
786 CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero));
787 } else if (Subtarget->isFP64bit()) {
788 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
790 ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64_64, DL,
793 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
795 ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64, DL,
805 int64_t Imm = CN->getSExtValue();
806 unsigned Size = CN->getValueSizeInBits(0);
819 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
825 if (Inst->Opc == Mips::LUi64)
826 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
829 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
830 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
835 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), DL,
837 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
846 const unsigned IntrinsicOpcode = Node->getConstantOperandVal(1);
852 SDValue ChainIn = Node->getOperand(0);
853 SDValue RegIdx = Node->getOperand(2);
854 SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
865 assert(Node->getNumOperands() == 4 && "Unexpected number of operands.");
866 const SDValue &Chain = Node->getOperand(0);
867 const SDValue &Intrinsic = Node->getOperand(1);
868 const SDValue &Pointer = Node->getOperand(2);
869 const SDValue &Constant = Node->getOperand(3);
879 cast<ConstantSDNode>(Constant)->getConstantIntValue();
881 CurDAG->getTargetConstant(*Val, DL, Constant.getValueType());
885 assert(Node->getNumValues() == 2);
886 assert(Node->getValueType(0).is128BitVector());
887 assert(Node->getValueType(1) == MVT::Other);
888 SmallVector<EVT, 2> ResTys{Node->getValueType(0), Node->getValueType(1)};
890 ReplaceNode(Node, CurDAG->getMachineNode(Op, DL, ResTys, Ops));
899 switch (Node->getConstantOperandVal(0)) {
906 ReplaceNode(Node, CurDAG->getMachineNode(Mips::MOVE_V, DL,
907 Node->getValueType(0),
908 Node->getOperand(1)));
915 const unsigned IntrinsicOpcode = Node->getConstantOperandVal(1);
921 SDValue ChainIn = Node->getOperand(0);
922 SDValue RegIdx = Node->getOperand(2);
923 SDValue Value = Node->getOperand(3);
924 SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
935 assert(Node->getNumOperands() == 5 && "Unexpected number of operands.");
936 const SDValue &Chain = Node->getOperand(0);
937 const SDValue &Intrinsic = Node->getOperand(1);
938 const SDValue &Vec = Node->getOperand(2);
939 const SDValue &Pointer = Node->getOperand(3);
940 const SDValue &Constant = Node->getOperand(4);
950 cast<ConstantSDNode>(Constant)->getConstantIntValue();
952 CurDAG->getTargetConstant(*Val, DL, Constant.getValueType());
956 assert(Node->getNumValues() == 1);
957 assert(Node->getValueType(0) == MVT::Other);
958 SmallVector<EVT, 1> ResTys{Node->getValueType(0)};
960 ReplaceNode(Node, CurDAG->getMachineNode(Op, DL, ResTys, Ops));
968 MVT ResTy = Node->getSimpleValueType(0);
973 Opc = (Subtarget->isFP64bit() ? Mips::FABS_D64 : Mips::FABS_D32);
977 if (Subtarget->inMicroMipsMode()) {
994 CurDAG->getMachineNode(Opc, DL, ResTy, Node->getOperand(0)));
1008 if (Node->getValueType(0) != MVT::i32 && Node->getValueType(0) != MVT::i64)
1011 if (Node->getNumOperands() != 4)
1014 if (Node->getOperand(1)->getOpcode() != ISD::Constant ||
1015 Node->getOperand(2)->getOpcode() != ISD::Constant)
1018 MVT ResTy = Node->getSimpleValueType(0);
1019 uint64_t Pos = Node->getConstantOperandVal(1);
1020 uint64_t Size = Node->getConstantOperandVal(2);
1047 Node->getOperand(0), CurDAG->getTargetConstant(Pos, DL, MVT::i32),
1048 CurDAG->getTargetConstant(Size, DL, MVT::i32), Node->getOperand(3)};
1050 ReplaceNode(Node, CurDAG->getMachineNode(Opcode, DL, ResTy, Ops));
1058 EVT PtrVT = getTargetLowering()->getPointerTy(CurDAG->getDataLayout());
1070 CurDAG->getMachineNode(RdhwrOpc, DL, Node->getValueType(0), MVT::Glue,
1071 CurDAG->getRegister(Mips::HWR29, MVT::i32),
1072 CurDAG->getTargetConstant(0, DL, MVT::i32));
1073 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
1075 SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT,
1083 // 128-bit when MSA is enabled. Fixup any register class mismatches that
1089 // 0x01010101 } without using a constant pool. This would be sub-optimal
1090 // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
1102 EVT ResVecTy = BVN->getValueType(0);
1105 if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
1108 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
1110 !Subtarget->isLittle()))
1141 SDValue Imm = CurDAG->getTargetConstant(SplatValue, DL,
1144 Res = CurDAG->getMachineNode(LdiOp, DL, ViaVecTy, Imm);
1156 SDValue ZeroVal = CurDAG->getRegister(
1170 SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, SplatMVT);
1172 Res = CurDAG->getMachineNode(ADDiuOp, DL, SplatMVT, ZeroVal, LoVal);
1173 Res = CurDAG->getMachineNode(FILLOp, DL, ViaVecTy, SDValue(Res, 0));
1179 const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1180 SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1182 SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1183 SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1185 if (Hi)
1186 Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1189 Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1190 Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1192 assert((Hi || Lo) && "Zero case reached 32 bit case splat synthesis!");
1194 CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32, SDValue(Res, 0));
1202 const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1203 SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1205 SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1206 SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1208 if (Hi)
1209 Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1212 Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1213 Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1215 Res = CurDAG->getMachineNode(
1217 CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64),
1219 CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1222 CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
1231 // lui $res2, %hi(val) lui $res2, %hi(val)
1244 // daui $res, $res, %hi(val)
1251 const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1255 SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1256 SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1257 SDValue HigherVal = CurDAG->getTargetConstant(Higher, DL, MVT::i32);
1258 SDValue HighestVal = CurDAG->getTargetConstant(Highest, DL, MVT::i32);
1259 SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1277 if (Hi)
1278 Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1281 Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1282 Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1286 HiRes = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HighestVal);
1289 HiRes = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1295 Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32,
1296 (Hi || Lo) ? SDValue(Res, 0) : ZeroVal);
1298 Res = CurDAG->getMachineNode(
1301 CurDAG->getTargetConstant(1, DL, MVT::i32));
1305 TLI->getRegClassFor(ViaVecTy.getSimpleVT());
1307 Res = CurDAG->getMachineNode(
1309 CurDAG->getTargetConstant(RC->getID(), DL, MVT::i32));
1311 Res = CurDAG->getMachineNode(
1313 CurDAG->getTargetConstant(0, DL, MVT::i32));
1316 SDValue Zero64Val = CurDAG->getRegister(Mips::ZERO_64, MVT::i64);
1318 const bool ResNonZero = Hi || Lo;
1321 HiRes = CurDAG->getMachineNode(
1323 CurDAG->getTargetConstant(((Highest >> 15) & 0x1), DL, MVT::i64),
1325 CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1328 Res = CurDAG->getMachineNode(
1330 CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64),
1332 CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1343 IntegerType::get(MF->getFunction().getContext(), 32);
1346 CurDAG->getConstant(*Const32, DL, MVT::i32),
1347 CurDAG->getConstant(*Const32, DL, MVT::i32),
1350 Res = CurDAG->getMachineNode(Mips::DINSU, DL, MVT::i64, Ops);
1352 Res = CurDAG->getMachineNode(
1354 CurDAG->getTargetConstant(0, DL, MVT::i32));
1357 "Zero splat value handled by non-zero 64bit splat synthesis!");
1359 Res = CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64,
1374 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
1375 Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, DL,
1377 CurDAG->getTargetConstant(RC->getID(), DL,
1407 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1413 // For now, support 9-bit signed offsets which is supportable by all
1421 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1426 if (Subtarget->inMicroMipsMode()) {
1427 // On microMIPS, they can handle 12-bit offsets.
1433 } else if (Subtarget->hasMips32r6()) {
1434 // On MIPS32r6/MIPS64r6, they can only handle 9-bit offsets.
1441 // Prior to MIPS32r6/MIPS64r6, they can handle 16-bit offsets.
1446 // In all cases, 0-bit offsets are acceptable.
1448 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));