Lines Matching +full:hi +full:- +full:fi
1 //===- MipsSEFrameLowering.cpp - Mips32/64 Frame Information --------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
116 switch(I->getOpcode()) {
168 // load $vr, FI
171 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
175 Register Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
177 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
178 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
184 // store $vr, FI
186 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
190 Register Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
192 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
193 .addReg(Src, getKillRegState(I->getOperand(0).isKill()));
194 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
199 // load $vr0, FI
201 // load $vr1, FI + 4
202 // copy hi, $vr1
204 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
209 Register Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
211 Register Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
212 DebugLoc DL = I->getDebugLoc();
215 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0);
217 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
218 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
225 // store $vr0, FI
227 // store $vr1, FI + 4
229 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
234 Register Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
235 unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
236 DebugLoc DL = I->getDebugLoc();
239 TII.storeRegToStack(MBB, I, VR0, true, FI, RC, &RegInfo, 0);
241 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize);
245 Register Src = I->getOperand(1).getReg();
261 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
267 unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
270 DebugLoc DL = I->getDebugLoc();
296 // for odd-numbered double precision values (because the lower 32-bits is
300 // double-precision values in regardless of being an odd/even register.
305 if (I->getNumOperands() == 4 && I->getOperand(3).isReg()
306 && I->getOperand(3).getReg() == Mips::SP) {
307 Register DstReg = I->getOperand(0).getReg();
308 Register LoReg = I->getOperand(1).getReg();
309 Register HiReg = I->getOperand(2).getReg();
311 // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
312 // the cases where mthc1 is not available). 64-bit architectures and
321 // We re-use the same spill slot each time so that the stack frame doesn't
323 int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(MF, RC2);
326 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC,
328 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC,
330 TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, 0);
345 const MachineOperand &Op1 = I->getOperand(1);
346 const MachineOperand &Op2 = I->getOperand(2);
349 Register DstReg = I->getOperand(0).getReg();
350 BuildMI(MBB, I, I->getDebugLoc(), TII.get(Mips::IMPLICIT_DEF), DstReg);
361 // for odd-numbered double precision values (because the lower 32-bits is
365 // double-precision values in regardless of being an odd/even register.
370 if (I->getNumOperands() == 4 && I->getOperand(3).isReg()
371 && I->getOperand(3).getReg() == Mips::SP) {
372 Register DstReg = I->getOperand(0).getReg();
375 int64_t Offset = 4 * (Subtarget.isLittle() ? N : (1 - N));
377 // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
378 // the cases where mfhc1 is not available). 64-bit architectures and
387 // We re-use the same spill slot each time so that the stack frame doesn't
389 int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(MF, RC);
390 TII.storeRegToStack(MBB, I, SrcReg, Op1.isKill(), FI, RC, &RegInfo, 0);
391 TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, Offset);
433 TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
447 // Find the instruction past the last instruction that saves a callee-saved
452 // Iterate over list of callee-saved registers and emit .cfi_offset
462 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);
464 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);
479 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true);
480 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1;
497 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
504 if (MipsFI->callsEhReturn()) {
510 MipsFI->getEhDataRegFI(I), RC, &RegInfo,
516 int64_t Offset = MFI.getObjectOffset(MipsFI->getEhDataRegFI(I));
517 unsigned Reg = MRI->getDwarfRegNum(ABI.GetEhDataReg(I), true);
533 nullptr, MRI->getDwarfRegNum(FP, true)));
538 // addiu $Reg, $zero, -MaxAlignment
543 int64_t MaxAlign = -(int64_t)MFI.getMaxAlign().value();
563 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
572 "\"interrupt\" attribute is not supported on pre-MIPS32R2 or "
597 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K0)
602 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EXT), Mips::K0)
611 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)
616 STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false,
617 MipsFI->getISRRegFI(0), PtrRC,
622 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)
627 STI.getInstrInfo()->storeRegToStack(MBB, MBBI, Mips::K1, false,
628 MipsFI->getISRRegFI(1), PtrRC,
656 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
664 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
673 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
681 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
698 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
707 // Find the first instruction that restores a callee-saved register.
711 --I;
717 if (MipsFI->callsEhReturn()) {
721 // Find first instruction that restores a callee-saved register.
724 --I;
729 MipsFI->getEhDataRegFI(J), RC, &RegInfo,
751 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
757 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::DI), Mips::ZERO);
758 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EHB));
761 STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1,
762 MipsFI->getISRRegFI(0), PtrRC,
764 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP014)
769 STI.getInstrInfo()->loadRegFromStackSlot(MBB, MBBI, Mips::K1,
770 MipsFI->getISRRegFI(1), PtrRC,
772 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
778 MipsSEFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
783 if (MFI.isFixedObjectIndex(FI))
788 return StackOffset::getFixed(MFI.getObjectOffset(FI) + MFI.getStackSize() -
800 // Add the callee-saved register as live-in. Do not add if the register is
807 && MF->getFrameInfo().isReturnAddressTaken();
811 // ISRs require HI/LO to be spilled into kernel registers to be then
815 const Function &Func = MBB.getParent()->getFunction();
817 DebugLoc DL = MI->getDebugLoc();
833 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
844 // Reserve call frame if the size of the maximum call frame fits into 16-bit
881 if (MipsFI->callsEhReturn())
882 MipsFI->createEhDataRegsFI(MF);
885 if (MipsFI->isISR())
886 MipsFI->createISRRegFI(MF);
892 // general-purpose registers 64 bits wide, it should be 64-bit, otherwise
893 // it should be 32-bit.
896 int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC),
897 TRI->getSpillAlign(RC), false);
898 RS->addScavengingFrameIndex(FI);
912 int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC),
913 TRI->getSpillAlign(RC), false);
914 RS->addScavengingFrameIndex(FI);