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1 //===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 let Inst{31-26} = 0b011110;
16 let Inst{31-26} = 0b010001;
20 let Inst{31-26} = 0b000000;
30 class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
35 let Inst{25-23} = major;
36 let Inst{22-19} = 0b1110;
37 let Inst{18-16} = m;
38 let Inst{15-11} = ws;
39 let Inst{10-6} = wd;
40 let Inst{5-0} = minor;
43 class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
48 let Inst{25-23} = major;
49 let Inst{22-20} = 0b110;
50 let Inst{19-16} = m;
51 let Inst{15-11} = ws;
52 let Inst{10-6} = wd;
53 let Inst{5-0} = minor;
56 class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
61 let Inst{25-23} = major;
62 let Inst{22-21} = 0b10;
63 let Inst{20-16} = m;
64 let Inst{15-11} = ws;
65 let Inst{10-6} = wd;
66 let Inst{5-0} = minor;
69 class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst {
72 bits<6> m;
74 let Inst{25-23} = major;
75 let Inst{22} = 0b0;
76 let Inst{21-16} = m;
77 let Inst{15-11} = ws;
78 let Inst{10-6} = wd;
79 let Inst{5-0} = minor;
82 class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
86 let Inst{25-18} = major;
87 let Inst{17-16} = df;
88 let Inst{15-11} = rs;
89 let Inst{10-6} = wd;
90 let Inst{5-0} = minor;
93 class MSA_2R_FILL_D_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
97 let Inst{25-18} = major;
98 let Inst{17-16} = df;
99 let Inst{15-11} = rs;
100 let Inst{10-6} = wd;
101 let Inst{5-0} = minor;
104 class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
108 let Inst{25-18} = major;
109 let Inst{17-16} = df;
110 let Inst{15-11} = ws;
111 let Inst{10-6} = wd;
112 let Inst{5-0} = minor;
115 class MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst {
119 let Inst{25-17} = major;
121 let Inst{15-11} = ws;
122 let Inst{10-6} = wd;
123 let Inst{5-0} = minor;
126 class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
131 let Inst{25-23} = major;
132 let Inst{22-21} = df;
133 let Inst{20-16} = wt;
134 let Inst{15-11} = ws;
135 let Inst{10-6} = wd;
136 let Inst{5-0} = minor;
139 class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst {
144 let Inst{25-22} = major;
146 let Inst{20-16} = wt;
147 let Inst{15-11} = ws;
148 let Inst{10-6} = wd;
149 let Inst{5-0} = minor;
152 class MSA_3R_INDEX_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
157 let Inst{25-23} = major;
158 let Inst{22-21} = df;
159 let Inst{20-16} = rt;
160 let Inst{15-11} = ws;
161 let Inst{10-6} = wd;
162 let Inst{5-0} = minor;
165 class MSA_ELM_FMT<bits<10> major, bits<6> minor>: MSAInst {
169 let Inst{25-16} = major;
170 let Inst{15-11} = ws;
171 let Inst{10-6} = wd;
172 let Inst{5-0} = minor;
175 class MSA_ELM_CFCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst {
179 let Inst{25-16} = major;
180 let Inst{15-11} = cs;
181 let Inst{10-6} = rd;
182 let Inst{5-0} = minor;
185 class MSA_ELM_CTCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst {
189 let Inst{25-16} = major;
190 let Inst{15-11} = rs;
191 let Inst{10-6} = cd;
192 let Inst{5-0} = minor;
195 class MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
200 let Inst{25-22} = major;
201 let Inst{21-20} = 0b00;
202 let Inst{19-16} = n{3-0};
203 let Inst{15-11} = ws;
204 let Inst{10-6} = wd;
205 let Inst{5-0} = minor;
208 class MSA_ELM_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
213 let Inst{25-22} = major;
214 let Inst{21-19} = 0b100;
215 let Inst{18-16} = n{2-0};
216 let Inst{15-11} = ws;
217 let Inst{10-6} = wd;
218 let Inst{5-0} = minor;
221 class MSA_ELM_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
226 let Inst{25-22} = major;
227 let Inst{21-18} = 0b1100;
228 let Inst{17-16} = n{1-0};
229 let Inst{15-11} = ws;
230 let Inst{10-6} = wd;
231 let Inst{5-0} = minor;
234 class MSA_ELM_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
239 let Inst{25-22} = major;
240 let Inst{21-17} = 0b11100;
241 let Inst{16} = n{0};
242 let Inst{15-11} = ws;
243 let Inst{10-6} = wd;
244 let Inst{5-0} = minor;
247 class MSA_ELM_COPY_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
252 let Inst{25-22} = major;
253 let Inst{21-20} = 0b00;
254 let Inst{19-16} = n{3-0};
255 let Inst{15-11} = ws;
256 let Inst{10-6} = rd;
257 let Inst{5-0} = minor;
260 class MSA_ELM_COPY_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
265 let Inst{25-22} = major;
266 let Inst{21-19} = 0b100;
267 let Inst{18-16} = n{2-0};
268 let Inst{15-11} = ws;
269 let Inst{10-6} = rd;
270 let Inst{5-0} = minor;
273 class MSA_ELM_COPY_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
278 let Inst{25-22} = major;
279 let Inst{21-18} = 0b1100;
280 let Inst{17-16} = n{1-0};
281 let Inst{15-11} = ws;
282 let Inst{10-6} = rd;
283 let Inst{5-0} = minor;
286 class MSA_ELM_COPY_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
291 let Inst{25-22} = major;
292 let Inst{21-17} = 0b11100;
293 let Inst{16} = n{0};
294 let Inst{15-11} = ws;
295 let Inst{10-6} = rd;
296 let Inst{5-0} = minor;
299 class MSA_ELM_INSERT_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
300 bits<6> n;
304 let Inst{25-22} = major;
305 let Inst{21-20} = 0b00;
306 let Inst{19-16} = n{3-0};
307 let Inst{15-11} = rs;
308 let Inst{10-6} = wd;
309 let Inst{5-0} = minor;
312 class MSA_ELM_INSERT_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
313 bits<6> n;
317 let Inst{25-22} = major;
318 let Inst{21-19} = 0b100;
319 let Inst{18-16} = n{2-0};
320 let Inst{15-11} = rs;
321 let Inst{10-6} = wd;
322 let Inst{5-0} = minor;
325 class MSA_ELM_INSERT_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
326 bits<6> n;
330 let Inst{25-22} = major;
331 let Inst{21-18} = 0b1100;
332 let Inst{17-16} = n{1-0};
333 let Inst{15-11} = rs;
334 let Inst{10-6} = wd;
335 let Inst{5-0} = minor;
338 class MSA_ELM_INSERT_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
339 bits<6> n;
343 let Inst{25-22} = major;
344 let Inst{21-17} = 0b11100;
345 let Inst{16} = n{0};
346 let Inst{15-11} = rs;
347 let Inst{10-6} = wd;
348 let Inst{5-0} = minor;
351 class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
356 let Inst{25-23} = major;
357 let Inst{22-21} = df;
358 let Inst{20-16} = imm;
359 let Inst{15-11} = ws;
360 let Inst{10-6} = wd;
361 let Inst{5-0} = minor;
364 class MSA_I8_FMT<bits<2> major, bits<6> minor>: MSAInst {
369 let Inst{25-24} = major;
370 let Inst{23-16} = u8;
371 let Inst{15-11} = ws;
372 let Inst{10-6} = wd;
373 let Inst{5-0} = minor;
376 class MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
380 let Inst{25-23} = major;
381 let Inst{22-21} = df;
382 let Inst{20-11} = s10;
383 let Inst{10-6} = wd;
384 let Inst{5-0} = minor;
391 let Inst{25-16} = addr{9-0};
392 let Inst{15-11} = addr{20-16};
393 let Inst{10-6} = wd;
394 let Inst{5-2} = minor;
395 let Inst{1-0} = df;
398 class MSA_VEC_FMT<bits<5> major, bits<6> minor>: MSAInst {
403 let Inst{25-21} = major;
404 let Inst{20-16} = wt;
405 let Inst{15-11} = ws;
406 let Inst{10-6} = wd;
407 let Inst{5-0} = minor;
414 let Inst{25-23} = major;
415 let Inst{22-21} = df;
416 let Inst{20-16} = wt;
417 let Inst{15-0} = offset;
424 let Inst{25-21} = major;
425 let Inst{20-16} = wt;
426 let Inst{15-0} = offset;
429 class SPECIAL_LSA_FMT<bits<6> minor>: MSASpecial {
435 let Inst{25-21} = rs;
436 let Inst{20-16} = rt;
437 let Inst{15-11} = rd;
438 let Inst{10-8} = 0b000;
439 let Inst{7-6} = sa;
440 let Inst{5-0} = minor;
443 class SPECIAL_DLSA_FMT<bits<6> minor>: MSASpecial {
449 let Inst{25-21} = rs;
450 let Inst{20-16} = rt;
451 let Inst{15-11} = rd;
452 let Inst{10-8} = 0b000;
453 let Inst{7-6} = sa;
454 let Inst{5-0} = minor;