Lines Matching defs:ST
68 MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
83 .legalIf([=, &ST](const LegalityQuery &Query) {
86 if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64}))
107 .legalIf([=, &ST](const LegalityQuery &Query) {
110 {s32, p0, 16, ST.systemSupportsUnalignedAccess()},
113 {s64, p0, 64, ST.systemSupportsUnalignedAccess()}}))
115 if (ST.hasMSA() && CheckTy0Ty1MemSizeAlign(
126 .customIf([=, &ST](const LegalityQuery &Query) {
141 if (!ST.systemSupportsUnalignedAccess() &&
199 .legalIf([=, &ST](const LegalityQuery &Query) {
202 if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64}))
242 .legalIf([=, &ST](const LegalityQuery &Query) {
243 if (ST.hasMips32r2() && CheckTyN(0, Query, {s32}))
247 .lowerIf([=, &ST](const LegalityQuery &Query) {
248 if (!ST.hasMips32r2() && CheckTyN(0, Query, {s32}))
282 .legalIf([=, &ST](const LegalityQuery &Query) {
285 if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64}))
330 verify(*ST.getInstrInfo());
471 const MipsSubtarget &ST) {
472 assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
477 .constrainAllUses(MIRBuilder.getTII(), *ST.getRegisterInfo(),
478 *ST.getRegBankInfo()))
486 const MipsSubtarget &ST) {
487 assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
498 const MipsSubtarget &ST) {
499 assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
510 const MipsSubtarget &ST = MI.getMF()->getSubtarget<MipsSubtarget>();
530 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_ADD, MIRBuilder, ST);
532 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_B, MIRBuilder, ST);
534 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_H, MIRBuilder, ST);
536 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_W, MIRBuilder, ST);
538 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_D, MIRBuilder, ST);
543 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_SUB, MIRBuilder, ST);
545 return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_B, MIRBuilder, ST);
547 return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_H, MIRBuilder, ST);
549 return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_W, MIRBuilder, ST);
551 return SelectMSA3OpIntrinsic(MI, Mips::SUBVI_D, MIRBuilder, ST);
556 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_MUL, MIRBuilder, ST);
561 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_SDIV, MIRBuilder, ST);
566 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_SREM, MIRBuilder, ST);
571 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_UDIV, MIRBuilder, ST);
576 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_UREM, MIRBuilder, ST);
579 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FADD, MIRBuilder, ST);
582 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FSUB, MIRBuilder, ST);
585 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FMUL, MIRBuilder, ST);
588 return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FDIV, MIRBuilder, ST);
590 return SelectMSA3OpIntrinsic(MI, Mips::FMAX_A_W, MIRBuilder, ST);
592 return SelectMSA3OpIntrinsic(MI, Mips::FMAX_A_D, MIRBuilder, ST);
594 return MSA2OpIntrinsicToGeneric(MI, TargetOpcode::G_FSQRT, MIRBuilder, ST);
596 return MSA2OpIntrinsicToGeneric(MI, TargetOpcode::G_FSQRT, MIRBuilder, ST);