Lines Matching +full:32 +full:- +full:bits
1 //===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
14 // opcode - operation code.
15 // rs - src reg.
16 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
17 // rd - dst reg, only used on 3 regs instr.
18 // shamt - only used on shift instructions, contains the shift amount.
19 // funct - combined with opcode field give us an operation code.
21 //===----------------------------------------------------------------------===//
24 // ad-hoc solution used to emit machine instruction encodings by our machine
26 class Format<bits<4> val> {
27 bits<4> Value = val;
74 field bits<32> Inst;
81 bits<6> Opcode = 0;
83 // Top 6 bits are the 'opcode' field
84 let Inst{31-26} = Opcode;
96 bits<4> FormBits = Form.Value;
101 // present in MIPS-I to MIPS-III.
104 let TSFlags{3-0} = FormBits;
111 field bits<32> SoftFail = 0;
138 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
147 //===----------------------------------------------------------------------===//
149 //===----------------------------------------------------------------------===//
151 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
155 bits<5> rd;
156 bits<5> rs;
157 bits<5> rt;
158 bits<5> shamt;
159 bits<6> funct;
164 let Inst{25-21} = rs;
165 let Inst{20-16} = rt;
166 let Inst{15-11} = rd;
167 let Inst{10-6} = shamt;
168 let Inst{5-0} = funct;
171 //===----------------------------------------------------------------------===//
173 //===----------------------------------------------------------------------===//
175 class FJ<bits<6> op> : StdArch
177 bits<26> target;
179 bits<32> Inst;
181 let Inst{31-26} = op;
182 let Inst{25-0} = target;
185 //===----------------------------------------------------------------------===//
187 //===----------------------------------------------------------------------===//
188 class MFC3OP_FM<bits<6> op, bits<5> mfmt, bits<3> guest> : StdArch {
189 bits<5> rt;
190 bits<5> rd;
191 bits<3> sel;
193 bits<32> Inst;
195 let Inst{31-26} = op;
196 let Inst{25-21} = mfmt;
197 let Inst{20-16} = rt;
198 let Inst{15-11} = rd;
199 let Inst{10-8} = guest;
200 let Inst{7-3} = 0;
201 let Inst{2-0} = sel;
204 class MFC2OP_FM<bits<6> op, bits<5> mfmt> : StdArch {
205 bits<5> rt;
206 bits<16> imm16;
208 bits<32> Inst;
210 let Inst{31-26} = op;
211 let Inst{25-21} = mfmt;
212 let Inst{20-16} = rt;
213 let Inst{15-0} = imm16;
216 class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
217 bits<5> rd;
218 bits<5> rs;
219 bits<5> rt;
221 bits<32> Inst;
223 let Inst{31-26} = op;
224 let Inst{25-21} = rs;
225 let Inst{20-16} = rt;
226 let Inst{15-11} = rd;
227 let Inst{10-6} = 0;
228 let Inst{5-0} = funct;
231 class ADDI_FM<bits<6> op> : StdArch {
232 bits<5> rs;
233 bits<5> rt;
234 bits<16> imm16;
236 bits<32> Inst;
238 let Inst{31-26} = op;
239 let Inst{25-21} = rs;
240 let Inst{20-16} = rt;
241 let Inst{15-0} = imm16;
244 class SRA_FM<bits<6> funct, bit rotate> : StdArch {
245 bits<5> rd;
246 bits<5> rt;
247 bits<5> shamt;
249 bits<32> Inst;
251 let Inst{31-26} = 0;
252 let Inst{25-22} = 0;
254 let Inst{20-16} = rt;
255 let Inst{15-11} = rd;
256 let Inst{10-6} = shamt;
257 let Inst{5-0} = funct;
260 class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
261 bits<5> rd;
262 bits<5> rt;
263 bits<5> rs;
265 bits<32> Inst;
267 let Inst{31-26} = 0;
268 let Inst{25-21} = rs;
269 let Inst{20-16} = rt;
270 let Inst{15-11} = rd;
271 let Inst{10-7} = 0;
273 let Inst{5-0} = funct;
276 class BEQ_FM<bits<6> op> : StdArch {
277 bits<5> rs;
278 bits<5> rt;
279 bits<16> offset;
281 bits<32> Inst;
283 let Inst{31-26} = op;
284 let Inst{25-21} = rs;
285 let Inst{20-16} = rt;
286 let Inst{15-0} = offset;
289 class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch {
290 bits<5> rs;
291 bits<16> offset;
293 bits<32> Inst;
295 let Inst{31-26} = op;
296 let Inst{25-21} = rs;
297 let Inst{20-16} = funct;
298 let Inst{15-0} = offset;
301 class BBIT_FM<bits<6> op> : StdArch {
302 bits<5> rs;
303 bits<5> p;
304 bits<16> offset;
306 bits<32> Inst;
308 let Inst{31-26} = op;
309 let Inst{25-21} = rs;
310 let Inst{20-16} = p;
311 let Inst{15-0} = offset;
314 class SLTI_FM<bits<6> op> : StdArch {
315 bits<5> rt;
316 bits<5> rs;
317 bits<16> imm16;
319 bits<32> Inst;
321 let Inst{31-26} = op;
322 let Inst{25-21} = rs;
323 let Inst{20-16} = rt;
324 let Inst{15-0} = imm16;
327 class MFLO_FM<bits<6> funct> : StdArch {
328 bits<5> rd;
330 bits<32> Inst;
332 let Inst{31-26} = 0;
333 let Inst{25-16} = 0;
334 let Inst{15-11} = rd;
335 let Inst{10-6} = 0;
336 let Inst{5-0} = funct;
339 class MTLO_FM<bits<6> funct> : StdArch {
340 bits<5> rs;
342 bits<32> Inst;
344 let Inst{31-26} = 0;
345 let Inst{25-21} = rs;
346 let Inst{20-6} = 0;
347 let Inst{5-0} = funct;
350 class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch {
351 bits<5> rd;
352 bits<5> rt;
354 bits<32> Inst;
356 let Inst{31-26} = 0x1f;
357 let Inst{25-21} = 0;
358 let Inst{20-16} = rt;
359 let Inst{15-11} = rd;
360 let Inst{10-6} = funct;
361 let Inst{5-0} = funct2;
364 class CLO_FM<bits<6> funct> : StdArch {
365 bits<5> rd;
366 bits<5> rs;
367 bits<5> rt;
369 bits<32> Inst;
371 let Inst{31-26} = 0x1c;
372 let Inst{25-21} = rs;
373 let Inst{20-16} = rt;
374 let Inst{15-11} = rd;
375 let Inst{10-6} = 0;
376 let Inst{5-0} = funct;
381 bits<5> rt;
382 bits<16> imm16;
384 bits<32> Inst;
386 let Inst{31-26} = 0xf;
387 let Inst{25-21} = 0;
388 let Inst{20-16} = rt;
389 let Inst{15-0} = imm16;
393 bits<5> rd;
394 bits<5> rs;
396 bits<32> Inst;
398 let Inst{31-26} = 0;
399 let Inst{25-21} = rs;
400 let Inst{20-16} = 0;
401 let Inst{15-11} = rd;
402 let Inst{10-6} = 0;
403 let Inst{5-0} = 9;
406 class BGEZAL_FM<bits<5> funct> : StdArch {
407 bits<5> rs;
408 bits<16> offset;
410 bits<32> Inst;
412 let Inst{31-26} = 1;
413 let Inst{25-21} = rs;
414 let Inst{20-16} = funct;
415 let Inst{15-0} = offset;
419 bits<5> stype;
421 bits<32> Inst;
423 let Inst{31-26} = 0;
424 let Inst{10-6} = stype;
425 let Inst{5-0} = 0xf;
430 bits<21> addr;
431 bits<5> rs = addr{20-16};
432 bits<16> offset = addr{15-0};
434 bits<32> Inst;
436 let Inst{31-26} = 0b000001;
437 let Inst{25-21} = rs;
438 let Inst{20-16} = 0b11111;
439 let Inst{15-0} = offset;
442 class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
443 bits<5> rs;
444 bits<5> rt;
446 bits<32> Inst;
448 let Inst{31-26} = op;
449 let Inst{25-21} = rs;
450 let Inst{20-16} = rt;
451 let Inst{15-6} = 0;
452 let Inst{5-0} = funct;
455 class EXT_FM<bits<6> funct> : StdArch {
456 bits<5> rt;
457 bits<5> rs;
458 bits<5> pos;
459 bits<5> size;
461 bits<32> Inst;
463 let Inst{31-26} = 0x1f;
464 let Inst{25-21} = rs;
465 let Inst{20-16} = rt;
466 let Inst{15-11} = size;
467 let Inst{10-6} = pos;
468 let Inst{5-0} = funct;
472 bits<5> rt;
473 bits<5> rd;
474 bits<3> sel;
476 bits<32> Inst;
478 let Inst{31-26} = 0x1f;
479 let Inst{25-21} = 0;
480 let Inst{20-16} = rt;
481 let Inst{15-11} = rd;
482 let Inst{10-9} = 0b00;
483 let Inst{8-6} = sel;
484 let Inst{5-0} = 0x3b;
487 class TEQ_FM<bits<6> funct> : StdArch {
488 bits<5> rs;
489 bits<5> rt;
490 bits<10> code_;
492 bits<32> Inst;
494 let Inst{31-26} = 0;
495 let Inst{25-21} = rs;
496 let Inst{20-16} = rt;
497 let Inst{15-6} = code_;
498 let Inst{5-0} = funct;
501 class TEQI_FM<bits<5> funct> : StdArch {
502 bits<5> rs;
503 bits<16> imm16;
505 bits<32> Inst;
507 let Inst{31-26} = 1;
508 let Inst{25-21} = rs;
509 let Inst{20-16} = funct;
510 let Inst{15-0} = imm16;
514 bits<32> Inst;
516 let Inst{31-26} = 0x10;
518 let Inst{24-6} = 0;
519 let Inst{5-0} = 0x20;
522 class EXTS_FM<bits<6> funct> : StdArch {
523 bits<5> rt;
524 bits<5> rs;
525 bits<5> pos;
526 bits<5> lenm1;
528 bits<32> Inst;
530 let Inst{31-26} = 0x1c;
531 let Inst{25-21} = rs;
532 let Inst{20-16} = rt;
533 let Inst{15-11} = lenm1;
534 let Inst{10-6} = pos;
535 let Inst{5-0} = funct;
538 class MTMR_FM<bits<6> funct> : StdArch {
539 bits<5> rs;
541 bits<32> Inst;
543 let Inst{31-26} = 0x1c;
544 let Inst{25-21} = rs;
545 let Inst{20-6} = 0;
546 let Inst{5-0} = funct;
549 class POP_FM<bits<6> funct> : StdArch {
550 bits<5> rd;
551 bits<5> rs;
553 bits<32> Inst;
555 let Inst{31-26} = 0x1c;
556 let Inst{25-21} = rs;
557 let Inst{20-16} = 0;
558 let Inst{15-11} = rd;
559 let Inst{10-6} = 0;
560 let Inst{5-0} = funct;
563 class SEQ_FM<bits<6> funct> : StdArch {
564 bits<5> rd;
565 bits<5> rs;
566 bits<5> rt;
568 bits<32> Inst;
570 let Inst{31-26} = 0x1c;
571 let Inst{25-21} = rs;
572 let Inst{20-16} = rt;
573 let Inst{15-11} = rd;
574 let Inst{10-6} = 0;
575 let Inst{5-0} = funct;
578 class SEQI_FM<bits<6> funct> : StdArch {
579 bits<5> rs;
580 bits<5> rt;
581 bits<10> imm10;
583 bits<32> Inst;
585 let Inst{31-26} = 0x1c;
586 let Inst{25-21} = rs;
587 let Inst{20-16} = rt;
588 let Inst{15-6} = imm10;
589 let Inst{5-0} = funct;
592 class SAA_FM<bits<6> funct> : StdArch {
593 bits<5> rt;
594 bits<5> rs;
596 bits<32> Inst;
598 let Inst{31-26} = 0x1c;
599 let Inst{25-21} = rs;
600 let Inst{20-16} = rt;
601 let Inst{15-6} = 0;
602 let Inst{5-0} = funct;
605 //===----------------------------------------------------------------------===//
607 //===----------------------------------------------------------------------===//
609 class SYS_FM<bits<6> funct> : StdArch
611 bits<20> code_;
612 bits<32> Inst;
613 let Inst{31-26} = 0x0;
614 let Inst{25-6} = code_;
615 let Inst{5-0} = funct;
618 //===----------------------------------------------------------------------===//
620 //===----------------------------------------------------------------------===//
622 class BRK_FM<bits<6> funct> : StdArch
624 bits<10> code_1;
625 bits<10> code_2;
626 bits<32> Inst;
627 let Inst{31-26} = 0x0;
628 let Inst{25-16} = code_1;
629 let Inst{15-6} = code_2;
630 let Inst{5-0} = funct;
633 //===----------------------------------------------------------------------===//
635 //===----------------------------------------------------------------------===//
637 class ER_FM<bits<6> funct, bit LLBit> : StdArch
639 bits<32> Inst;
640 let Inst{31-26} = 0x10;
642 let Inst{24-7} = 0;
644 let Inst{5-0} = funct;
647 //===----------------------------------------------------------------------===//
649 //===----------------------------------------------------------------------===//
651 class EI_FM<bits<1> sc> : StdArch
653 bits<32> Inst;
654 bits<5> rt;
655 let Inst{31-26} = 0x10;
656 let Inst{25-21} = 0xb;
657 let Inst{20-16} = rt;
658 let Inst{15-11} = 0xc;
659 let Inst{10-6} = 0;
661 let Inst{4-0} = 0;
664 //===----------------------------------------------------------------------===//
668 // opcode - operation code.
669 // fs - src reg.
670 // ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
671 // fd - dst reg, only used on 3 regs instr.
672 // fmt - double or single precision.
673 // funct - combined with opcode field give us an operation code.
675 //===----------------------------------------------------------------------===//
677 //===----------------------------------------------------------------------===//
679 //===----------------------------------------------------------------------===//
681 class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch {
682 bits<5> fd;
683 bits<5> fs;
684 bits<5> ft;
686 bits<32> Inst;
688 let Inst{31-26} = 0x11;
689 let Inst{25-21} = fmt;
690 let Inst{20-16} = ft;
691 let Inst{15-11} = fs;
692 let Inst{10-6} = fd;
693 let Inst{5-0} = funct;
696 class ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch {
697 bits<5> fd;
698 bits<5> fs;
700 bits<32> Inst;
702 let Inst{31-26} = 0x11;
703 let Inst{25-21} = fmt;
704 let Inst{20-16} = 0;
705 let Inst{15-11} = fs;
706 let Inst{10-6} = fd;
707 let Inst{5-0} = funct;
710 class MFC1_FM<bits<5> funct> : StdArch {
711 bits<5> rt;
712 bits<5> fs;
714 bits<32> Inst;
716 let Inst{31-26} = 0x11;
717 let Inst{25-21} = funct;
718 let Inst{20-16} = rt;
719 let Inst{15-11} = fs;
720 let Inst{10-0} = 0;
723 class LW_FM<bits<6> op> : StdArch {
724 bits<5> rt;
725 bits<21> addr;
727 bits<32> Inst;
729 let Inst{31-26} = op;
730 let Inst{25-21} = addr{20-16};
731 let Inst{20-16} = rt;
732 let Inst{15-0} = addr{15-0};
735 class MADDS_FM<bits<3> funct, bits<3> fmt> : StdArch {
736 bits<5> fd;
737 bits<5> fr;
738 bits<5> fs;
739 bits<5> ft;
741 bits<32> Inst;
743 let Inst{31-26} = 0x13;
744 let Inst{25-21} = fr;
745 let Inst{20-16} = ft;
746 let Inst{15-11} = fs;
747 let Inst{10-6} = fd;
748 let Inst{5-3} = funct;
749 let Inst{2-0} = fmt;
752 class LWXC1_FM<bits<6> funct> : StdArch {
753 bits<5> fd;
754 bits<5> base;
755 bits<5> index;
757 bits<32> Inst;
759 let Inst{31-26} = 0x13;
760 let Inst{25-21} = base;
761 let Inst{20-16} = index;
762 let Inst{15-11} = 0;
763 let Inst{10-6} = fd;
764 let Inst{5-0} = funct;
767 class SWXC1_FM<bits<6> funct> : StdArch {
768 bits<5> fs;
769 bits<5> base;
770 bits<5> index;
772 bits<32> Inst;
774 let Inst{31-26} = 0x13;
775 let Inst{25-21} = base;
776 let Inst{20-16} = index;
777 let Inst{15-11} = fs;
778 let Inst{10-6} = 0;
779 let Inst{5-0} = funct;
783 bits<3> fcc;
784 bits<16> offset;
786 bits<32> Inst;
788 let Inst{31-26} = 0x11;
789 let Inst{25-21} = 0x8;
790 let Inst{20-18} = fcc;
793 let Inst{15-0} = offset;
796 class CEQS_FM<bits<5> fmt> : StdArch {
797 bits<5> fs;
798 bits<5> ft;
799 bits<3> fcc;
800 bits<4> cond;
802 bits<32> Inst;
804 let Inst{31-26} = 0x11;
805 let Inst{25-21} = fmt;
806 let Inst{20-16} = ft;
807 let Inst{15-11} = fs;
808 let Inst{10-8} = fcc;
809 let Inst{7-4} = 0x3;
810 let Inst{3-0} = cond;
813 class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {
817 class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch {
818 bits<5> fd;
819 bits<5> fs;
820 bits<5> rt;
822 bits<32> Inst;
824 let Inst{31-26} = 0x11;
825 let Inst{25-21} = fmt;
826 let Inst{20-16} = rt;
827 let Inst{15-11} = fs;
828 let Inst{10-6} = fd;
829 let Inst{5-0} = funct;
833 bits<5> rd;
834 bits<5> rs;
835 bits<3> fcc;
837 bits<32> Inst;
839 let Inst{31-26} = 0;
840 let Inst{25-21} = rs;
841 let Inst{20-18} = fcc;
844 let Inst{15-11} = rd;
845 let Inst{10-6} = 0;
846 let Inst{5-0} = 1;
849 class CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch {
850 bits<5> fd;
851 bits<5> fs;
852 bits<3> fcc;
854 bits<32> Inst;
856 let Inst{31-26} = 0x11;
857 let Inst{25-21} = fmt;
858 let Inst{20-18} = fcc;
861 let Inst{15-11} = fs;
862 let Inst{10-6} = fd;
863 let Inst{5-0} = 0x11;
866 class BARRIER_FM<bits<5> op> : StdArch {
867 bits<32> Inst;
869 let Inst{31-26} = 0; // SPECIAL
870 let Inst{25-21} = 0;
871 let Inst{20-16} = 0; // rt = 0
872 let Inst{15-11} = 0; // rd = 0
873 let Inst{10-6} = op; // Operation
874 let Inst{5-0} = 0; // SLL
878 bits<20> code_;
880 bits<32> Inst;
882 let Inst{31-26} = 0b011100; // SPECIAL2
883 let Inst{25-6} = code_;
884 let Inst{5-0} = 0b111111; // SDBBP
887 class JR_HB_FM<bits<6> op> : StdArch{
888 bits<5> rs;
890 bits<32> Inst;
892 let Inst{31-26} = 0; // SPECIAL
893 let Inst{25-21} = rs;
894 let Inst{20-11} = 0;
896 let Inst{9-6} = 0;
897 let Inst{5-0} = op;
900 class JALR_HB_FM<bits<6> op> : StdArch {
901 bits<5> rd;
902 bits<5> rs;
904 bits<32> Inst;
906 let Inst{31-26} = 0; // SPECIAL
907 let Inst{25-21} = rs;
908 let Inst{20-16} = 0;
909 let Inst{15-11} = rd;
911 let Inst{9-6} = 0;
912 let Inst{5-0} = op;
915 class COP0_TLB_FM<bits<6> op> : StdArch {
916 bits<32> Inst;
918 let Inst{31-26} = 0x10; // COP0
920 let Inst{24-6} = 0;
921 let Inst{5-0} = op; // Operation
924 class CACHEOP_FM<bits<6> op> : StdArch {
925 bits<21> addr;
926 bits<5> hint;
927 bits<5> base = addr{20-16};
928 bits<16> offset = addr{15-0};
930 bits<32> Inst;
932 let Inst{31-26} = op;
933 let Inst{25-21} = base;
934 let Inst{20-16} = hint;
935 let Inst{15-0} = offset;
938 class HYPCALL_FM<bits<6> op> : StdArch {
939 bits<10> code_;
941 bits<32> Inst;
943 let Inst{31-26} = 0b010000;
945 let Inst{20-11} = code_;
946 let Inst{5-0} = op;