Lines Matching +full:software +full:- +full:dl
1 //===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
65 // Get the Highest (63-48) 16 bits from a 64-bit immediate
68 // Get the Higher (47-32) 16 bits from a 64-bit immediate
71 // Get the High 16 bits from a 32/64-bit immediate
75 // Get the Lower 16 bits from a 32/64-bit immediate
82 // Get the High 16 bits from a 32-bit immediate for accessing TLS.
113 // FP-to-int truncation node.
122 // Software Exception Return.
227 SHF, // 4-element set shuffle.
238 // Combined (XOR (OR $a, $b), -1)
245 // Double select nodes for machines without conditional-move.
262 //===--------------------------------------------------------------------===//
264 //===--------------------------------------------------------------------===//
276 /// createFastISel - This method returns a target specific FastISel object,
312 const DataLayout &DL) const override {
313 const Align ABIAlign = DL.getABITypeAlign(ArgTy);
314 if (ArgTy->isVectorTy())
323 /// LowerOperation - Provide custom lowering hooks for some operations.
326 /// ReplaceNodeResults - Replace the results of node with an illegal result
332 /// getTargetNodeName - This method returns the name of a target specific
336 /// getSetCCResultType - get the ISD::SETCC result ValueType
337 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
384 SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
387 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
390 DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
393 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
395 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
403 SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
406 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
408 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo);
412 // computing a global symbol's address in large-GOT mode:
416 SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty,
420 SDValue Hi = DAG.getNode(MipsISD::GotHi, DL, Ty,
422 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
423 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
425 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo);
429 // computing a symbol's address in non-PIC mode:
435 SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty,
439 return DAG.getNode(ISD::ADD, DL, Ty,
440 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
441 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
445 // computing a symbol's address in non-PIC mode for N64.
452 SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty,
458 DAG.getNode(MipsISD::Highest, DL, Ty,
462 DAG.getNode(ISD::ADD, DL, Ty, Highest,
463 DAG.getNode(MipsISD::Higher, DL, Ty, Higher));
464 SDValue Cst = DAG.getConstant(16, DL, MVT::i32);
465 SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
466 SDValue Add = DAG.getNode(ISD::ADD, DL, Ty, Shift,
467 DAG.getNode(MipsISD::Hi, DL, Ty, Hi));
468 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst);
470 return DAG.getNode(ISD::ADD, DL, Ty, Shift2,
471 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
475 // computing a symbol's address using gp-relative addressing:
479 SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty,
483 ISD::ADD, DL, Ty,
485 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel));
532 const SDLoc &dl, SelectionDAG &DAG,
563 /// isEligibleForTailCallOptimization - Check whether the call is eligible
570 /// copyByValArg - Copy argument registers which were used to pass a byval
573 void copyByValRegs(SDValue Chain, const SDLoc &DL,
581 /// passByValArg - Pass a byval argument in registers or on stack.
582 void passByValArg(SDValue Chain, const SDLoc &DL,
590 /// writeVarArgRegs - Write variable function arguments passed in registers
594 const SDLoc &DL, SelectionDAG &DAG,
600 const SDLoc &dl, SelectionDAG &DAG,
604 SDValue Arg, const SDLoc &DL, bool IsTailCall,
618 const SDLoc &dl, SelectionDAG &DAG) const override;
621 const SDLoc &DL, SelectionDAG &DAG) const;
633 /// This function parses registers that appear in inline-asm constraints.
642 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
661 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
670 /// isFPImmLegal - Returns true if the target can instruction select the
683 /// Emit a sign-extension using sll/sra, seb, or seh appropriately.