Lines Matching defs:TempReg

391     unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
392     emitInst(Mips::MTC1, DestReg).addReg(TempReg);
422     Register TempReg = createResultReg(RC);
423     emitInst(Mips::ADDiu, TempReg)
426     DestReg = TempReg;
648     Register TempReg = createResultReg(&Mips::GPR32RegClass);
649     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
650     emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
654     Register TempReg = createResultReg(&Mips::GPR32RegClass);
655     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
656     emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
666     Register TempReg = createResultReg(&Mips::GPR32RegClass);
667     emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
668     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
672     Register TempReg = createResultReg(&Mips::GPR32RegClass);
673     emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
674     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
684     Register TempReg = createResultReg(&Mips::GPR32RegClass);
685     emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
686     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
690     Register TempReg = createResultReg(&Mips::GPR32RegClass);
691     emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
692     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
1053   Register TempReg = createResultReg(RC);
1055   if (!ResultReg || !TempReg)
1058   emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
1060     .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1119   Register TempReg = createResultReg(&Mips::FGR32RegClass);
1123   emitInst(Opc, TempReg).addReg(SrcReg);
1124   emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1603         unsigned TempReg[3];
1604         for (unsigned &R : TempReg) {
1609         emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1610         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1611         emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[1]).addImm(0xFF);
1612         emitInst(Mips::OR, DestReg).addReg(TempReg[0]).addReg(TempReg[2]);
1618         Register TempReg = createResultReg(&Mips::GPR32RegClass);
1619         emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1620         emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1624         unsigned TempReg[8];
1625         for (unsigned &R : TempReg) {
1631         emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1632         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1633         emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1634         emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1636         emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1637         emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1639         emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1640         emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1641         emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1836   Register TempReg = createResultReg(&Mips::GPR32RegClass);
1837   emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1838   emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1971     Register TempReg = createResultReg(&Mips::GPR32RegClass);
1972     if (!TempReg)
1977     if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1980     Op0Reg = TempReg;
2097     Register TempReg = createResultReg(&Mips::GPR32RegClass);
2098     if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
2100     VReg = TempReg;
2107     unsigned TempReg =
2110     emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());