Lines Matching defs:DestReg

180   bool emitCmp(unsigned DestReg, const CmpInst *CI);
184   bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
187   bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
189   bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
191                        unsigned DestReg);
193                        unsigned DestReg);
390     Register DestReg = createResultReg(RC);
392     emitInst(Mips::MTC1, DestReg).addReg(TempReg);
393     return DestReg;
396     Register DestReg = createResultReg(RC);
400     emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
401     return DestReg;
411   Register DestReg = createResultReg(RC);
417   emitInst(Mips::LW, DestReg)
424         .addReg(DestReg)
426     DestReg = TempReg;
428   return DestReg;
433   Register DestReg = createResultReg(RC);
434   emitInst(Mips::LW, DestReg)
437   return DestReg;
1003   Register DestReg = createResultReg(&Mips::AFGR64RegClass);
1004   emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
1005   updateValueMap(I, DestReg);
1080   Register DestReg = createResultReg(&Mips::FGR32RegClass);
1081   if (!DestReg)
1084   emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1085   updateValueMap(I, DestReg);
1118   Register DestReg = createResultReg(&Mips::GPR32RegClass);
1124   emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1126   updateValueMap(I, DestReg);
1594     Register DestReg = createResultReg(&Mips::GPR32RegClass);
1595     if (DestReg == 0)
1599         emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1600         updateValueMap(II, DestReg);
1612         emitInst(Mips::OR, DestReg).addReg(TempReg[0]).addReg(TempReg[2]);
1613         updateValueMap(II, DestReg);
1620         emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1621         updateValueMap(II, DestReg);
1641         emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1642         updateValueMap(II, DestReg);
1722     Register DestReg = VA.getLocReg();
1724     if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1760             TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1824                                    unsigned DestReg) {
1838   emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1843                                    unsigned DestReg) {
1848     emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1851     emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1858                                unsigned DestReg) {
1862     return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1863   return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1867                                unsigned DestReg) {
1884   emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1889                               unsigned DestReg, bool IsZExt) {
1898     return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1899   return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1904   unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1905   bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1906   return Success ? DestReg : 0;
2109     Register DestReg = createResultReg(&Mips::GPR32RegClass);
2110     emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
2111     Addr.setReg(DestReg);