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1 //===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
23 def HasDSP : Predicate<"Subtarget->hasDSP()">,
25 def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">,
27 def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">,
43 def SPECIAL3_OPCODE : Field6<0b011111>;
44 def REGIMM_OPCODE : Field6<0b000001>;
59 class DSPInstAlias<string Asm, dag Result, bit Emit = 0b1>
64 // ADDU.QB sub-class format.
65 class ADDU_QB_FMT<bits<5> op> : DSPInst {
66 bits<5> rd;
67 bits<5> rs;
68 bits<5> rt;
72 let Inst{25-21} = rs;
73 let Inst{20-16} = rt;
74 let Inst{15-11} = rd;
75 let Inst{10-6} = op;
76 let Inst{5-0} = 0b010000;
79 class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
80 bits<5> rd;
81 bits<5> rs;
85 let Inst{25-21} = rs;
86 let Inst{20-16} = 0;
87 let Inst{15-11} = rd;
88 let Inst{10-6} = op;
89 let Inst{5-0} = 0b010000;
92 // CMPU.EQ.QB sub-class format.
93 class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
94 bits<5> rs;
95 bits<5> rt;
99 let Inst{25-21} = rs;
100 let Inst{20-16} = rt;
101 let Inst{15-11} = 0;
102 let Inst{10-6} = op;
103 let Inst{5-0} = 0b010001;
106 class CMP_EQ_QB_R3_FMT<bits<5> op> : DSPInst {
107 bits<5> rs;
108 bits<5> rt;
109 bits<5> rd;
113 let Inst{25-21} = rs;
114 let Inst{20-16} = rt;
115 let Inst{15-11} = rd;
116 let Inst{10-6} = op;
117 let Inst{5-0} = 0b010001;
120 class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst {
121 bits<5> rs;
122 bits<5> rt;
123 bits<5> sa;
127 let Inst{25-21} = rs;
128 let Inst{20-16} = rt;
129 let Inst{15-11} = sa;
130 let Inst{10-6} = op;
131 let Inst{5-0} = 0b010001;
134 // ABSQ_S.PH sub-class format.
135 class ABSQ_S_PH_R2_FMT<bits<5> op> : DSPInst {
136 bits<5> rd;
137 bits<5> rt;
141 let Inst{25-21} = 0;
142 let Inst{20-16} = rt;
143 let Inst{15-11} = rd;
144 let Inst{10-6} = op;
145 let Inst{5-0} = 0b010010;
149 class REPL_FMT<bits<5> op> : DSPInst {
150 bits<5> rd;
155 let Inst{25-16} = imm;
156 let Inst{15-11} = rd;
157 let Inst{10-6} = op;
158 let Inst{5-0} = 0b010010;
161 // SHLL.QB sub-class format.
162 class SHLL_QB_FMT<bits<5> op> : DSPInst {
163 bits<5> rd;
164 bits<5> rt;
165 bits<5> rs_sa;
169 let Inst{25-21} = rs_sa;
170 let Inst{20-16} = rt;
171 let Inst{15-11} = rd;
172 let Inst{10-6} = op;
173 let Inst{5-0} = 0b010011;
176 // LX sub-class format.
177 class LX_FMT<bits<5> op> : DSPInst {
178 bits<5> rd;
179 bits<5> base;
180 bits<5> index;
184 let Inst{25-21} = base;
185 let Inst{20-16} = index;
186 let Inst{15-11} = rd;
187 let Inst{10-6} = op;
188 let Inst{5-0} = 0b001010;
191 // ADDUH.QB sub-class format.
192 class ADDUH_QB_FMT<bits<5> op> : DSPInst {
193 bits<5> rd;
194 bits<5> rs;
195 bits<5> rt;
199 let Inst{25-21} = rs;
200 let Inst{20-16} = rt;
201 let Inst{15-11} = rd;
202 let Inst{10-6} = op;
203 let Inst{5-0} = 0b011000;
206 // APPEND sub-class format.
207 class APPEND_FMT<bits<5> op> : DSPInst {
208 bits<5> rt;
209 bits<5> rs;
210 bits<5> sa;
214 let Inst{25-21} = rs;
215 let Inst{20-16} = rt;
216 let Inst{15-11} = sa;
217 let Inst{10-6} = op;
218 let Inst{5-0} = 0b110001;
221 // DPA.W.PH sub-class format.
222 class DPA_W_PH_FMT<bits<5> op> : DSPInst {
224 bits<5> rs;
225 bits<5> rt;
229 let Inst{25-21} = rs;
230 let Inst{20-16} = rt;
231 let Inst{15-13} = 0;
232 let Inst{12-11} = ac;
233 let Inst{10-6} = op;
234 let Inst{5-0} = 0b110000;
237 // MULT sub-class format.
240 bits<5> rs;
241 bits<5> rt;
245 let Inst{25-21} = rs;
246 let Inst{20-16} = rt;
247 let Inst{15-13} = 0;
248 let Inst{12-11} = ac;
249 let Inst{10-6} = 0;
250 let Inst{5-0} = funct;
253 // MFHI sub-class format.
255 bits<5> rd;
258 let Inst{31-26} = 0;
259 let Inst{25-23} = 0;
260 let Inst{22-21} = ac;
261 let Inst{20-16} = 0;
262 let Inst{15-11} = rd;
263 let Inst{10-6} = 0;
264 let Inst{5-0} = funct;
267 // MTHI sub-class format.
269 bits<5> rs;
272 let Inst{31-26} = 0;
273 let Inst{25-21} = rs;
274 let Inst{20-13} = 0;
275 let Inst{12-11} = ac;
276 let Inst{10-6} = 0;
277 let Inst{5-0} = funct;
280 // EXTR.W sub-class format (type 1).
281 class EXTR_W_TY1_FMT<bits<5> op> : DSPInst {
282 bits<5> rt;
284 bits<5> shift_rs;
288 let Inst{25-21} = shift_rs;
289 let Inst{20-16} = rt;
290 let Inst{15-13} = 0;
291 let Inst{12-11} = ac;
292 let Inst{10-6} = op;
293 let Inst{5-0} = 0b111000;
296 // SHILO sub-class format.
297 class SHILO_R1_FMT<bits<5> op> : DSPInst {
303 let Inst{25-20} = shift;
304 let Inst{19-13} = 0;
305 let Inst{12-11} = ac;
306 let Inst{10-6} = op;
307 let Inst{5-0} = 0b111000;
310 class SHILO_R2_FMT<bits<5> op> : DSPInst {
312 bits<5> rs;
316 let Inst{25-21} = rs;
317 let Inst{20-13} = 0;
318 let Inst{12-11} = ac;
319 let Inst{10-6} = op;
320 let Inst{5-0} = 0b111000;
323 class RDDSP_FMT<bits<5> op> : DSPInst {
324 bits<5> rd;
329 let Inst{25-16} = mask;
330 let Inst{15-11} = rd;
331 let Inst{10-6} = op;
332 let Inst{5-0} = 0b111000;
335 class WRDSP_FMT<bits<5> op> : DSPInst {
336 bits<5> rs;
341 let Inst{25-21} = rs;
342 let Inst{20-11} = mask;
343 let Inst{10-6} = op;
344 let Inst{5-0} = 0b111000;
347 class BPOSGE32_FMT<bits<5> op> : DSPInst {
352 let Inst{25-21} = 0;
353 let Inst{20-16} = op;
354 let Inst{15-0} = offset;
357 // INSV sub-class format.
359 bits<5> rt;
360 bits<5> rs;
364 let Inst{25-21} = rs;
365 let Inst{20-16} = rt;
366 let Inst{15-6} = 0;
367 let Inst{5-0} = op;