Lines Matching full:rx
82 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm8),
87 FRI16_ins_base<op, asmstr, "\t$rx, $imm8 \t# 16 bit inst", itin>;
91 FRI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm8, i32imm:$size),
92 !strconcat(asmstr, "\t$rx, $imm8\t# 16 bit inst"), [], itin>;
96 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm8),
101 FRI16R_ins_base<op, asmstr, "\t$rx, $imm8 \t# 16 bit inst", itin>;
105 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm8),
106 !strconcat(asmstr, "\t$rx, $imm8\t# 16 bit inst"), [], itin> {
107 let Constraints = "$rx_ = $rx";
112 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm8),
113 !strconcat(asmstr, "\t$rx, $imm8 # 16 bit inst"), [], itin>;
121 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
122 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> {
181 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
182 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
193 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm16),
198 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm16", itin>;
202 FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm16),
207 FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm16", itin>;
210 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm16", itin>;
214 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm16),
215 !strconcat(asmstr, "\t$rx, $imm16"), [], itin>;
219 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm16, i32imm:$size),
220 !strconcat(asmstr, "\t$rx, $imm16"), [], itin>;
224 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm16),
225 !strconcat(asmstr, "\t$rx, $imm16"), [], itin> {
226 let Constraints = "$rx_ = $rx";
235 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins (MemOpnd $rx, $imm16):$addr),
240 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, (MemOpnd $rx, $imm16):$addr),
250 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins (MemOpnd $rx, $imm15):$addr),
257 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa6),
258 !strconcat(asmstr, "\t$rx, $ry, $sa6"), [], itin>;
265 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
266 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
277 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
278 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
308 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
309 !strconcat(asmstr, "\t$rx, $ry"), []>;
315 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
316 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
325 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
326 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
335 FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
336 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
340 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
341 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ;
347 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
348 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
351 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
352 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
357 FRR16<f, (outs CPU16Regs:$rx), (ins),
358 !strconcat(asmstr, "\t$rx"), [], itin>;
362 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
365 let Constraints = "$rx = $rz";
368 let rx=0 in
383 FRR_SF16<_funct, _subfunc, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_),
384 !strconcat(asmstr, "\t $rx"),
386 let Constraints = "$rx_ = $rx";
393 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
394 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
489 MipsPseudo16<(outs CPU16Regs:$rx), (ins simm32:$imm, simm32:$constid),
490 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
525 // Format: ADDIU rx, immediate MIPS16e
546 // Format: ADDIU rx, pc, immediate MIPS16e
571 // Format: ADDU rz, rx, ry MIPS16e
579 // Format: AND rx, ry MIPS16e
587 // Format: BEQZ rx, offset MIPS16e
595 // Format: BEQZ rx, offset MIPS16e
616 // Format: BNEZ rx, offset MIPS16e
623 // Format: BNEZ rx, offset MIPS16e
691 // Format: CMP rx, ry MIPS16e
700 // Format: CMPI rx, immediate MIPS16e
709 // Format: CMPI rx, immediate MIPS16e
719 // Format: DIV rx, ry MIPS16e
728 // Format: DIVU rx, ry MIPS16e
779 let rx = 0b000;
786 // Format: LB ry, offset(rx) MIPS16e
795 // Format: LBU ry, offset(rx) MIPS16e
805 // Format: LH ry, offset(rx) MIPS16e
814 // Format: LHU ry, offset(rx) MIPS16e
824 // Format: LI rx, immediate MIPS16e
831 // Format: LI rx, immediate MIPS16e
842 // Format: LW ry, offset(rx) MIPS16e
850 // Format: LW rx, offset(sp) MIPS16e
877 // Format: MFHI rx MIPS16e
889 // Format: MFLO rx MIPS16e
916 // Format: MULT rx, ry MIPS16e
927 // Format: MULTU rx, ry MIPS16e
938 // Format: NEG rx, ry MIPS16e
945 // Format: NOT rx, ry MIPS16e
952 // Format: OR rx, ry MIPS16e
1007 // Format: SB ry, offset(rx) MIPS16e
1016 // Format: SEB rx MIPS16e
1018 // Sign-extend least significant byte in register rx.
1024 // Format: SEH rx MIPS16e
1026 // Sign-extend least significant word in register rx.
1146 // Format: SH ry, offset(rx) MIPS16e
1155 // Format: SLL rx, ry, sa MIPS16e
1162 // Format: SLLV ry, rx MIPS16e
1168 // Format: SLTI rx, immediate MIPS16e
1178 // Format: SLTI rx, immediate MIPS16e
1189 // Format: SLTIU rx, immediate MIPS16e
1199 // Format: SLTI rx, immediate MIPS16e
1208 // Format: SLTIU rx, immediate MIPS16e
1215 // Format: SLT rx, ry MIPS16e
1225 // Format: SLTU rx, ry MIPS16e
1241 // Format: SRAV ry, rx MIPS16e
1250 // Format: SRA rx, ry, sa MIPS16e
1259 // Format: SRLV ry, rx MIPS16e
1268 // Format: SRL rx, ry, sa MIPS16e
1276 // Format: SUBU rz, rx, ry MIPS16e
1283 // Format: SW ry, offset(rx) MIPS16e
1291 // Format: SW rx, offset(sp) MIPS16e
1292 // Purpose: Store Word rx (SP-Relative)
1300 // Format: XOR rx, ry MIPS16e
1388 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rx),
1389 "jalrc\t$rx", [(MipsJmpLink CPU16Regs:$rx)], II_JALRC> {
1402 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1403 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
1406 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1407 (I CPU16Regs:$rx, imm_type:$imm16)>;
1435 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1436 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1441 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1442 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1446 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
1447 (BeqzRxImm16 CPU16Regs:$rx, bb:$targ16)
1454 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1455 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1462 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1463 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1469 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1470 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1477 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1478 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1482 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1483 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1490 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1491 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1498 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1499 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1503 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1504 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1508 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
1509 (BnezRxImm16 CPU16Regs:$rx, bb:$targ16)
1516 <(brcond CPU16Regs:$rx, bb:$targ16),
1517 (BnezRxImm16 CPU16Regs:$rx, bb:$targ16)
1526 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1527 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1534 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1535 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1543 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1544 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1559 <(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry),
1560 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1566 <(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry),
1567 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;