Lines Matching +full:mii +full:- +full:rt
1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
63 #define DEBUG_TYPE "mips-asm-parser"
80 ATReg = Opts->getATRegIndex();
81 Reorder = Opts->isReorder();
82 Macro = Opts->isMacro();
83 Features = Opts->getFeatures();
163 // Print a warning along with its fix-it message at the given range.
436 /// This should be used in pseudo-instruction expansions which need AT.
458 // --------------------------------------------------
460 // | -------------------------------------------------|
466 // --------------------------------------------------
478 AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
486 AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
495 AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
501 AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits());
506 AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits());
527 const MCInstrInfo &MII, const MCTargetOptions &Options)
528 : MCTargetAsmParser(Options, sti, MII),
552 report_fatal_error("-mno-odd-spreg requires the O32 ABI");
557 IsPicEnabled = getContext().getObjectFileInfo()->isPositionIndependent();
560 CpRestoreOffset = -1;
573 /// True if all of $fcc0 - $fcc7 exist for the current ISA.
588 if (!JalExpr->evaluateAsRelocatable(Res, nullptr, nullptr))
807 /// MipsOperand - Instances of this class represent a parsed Mips machine
906 Op->RegIdx.Index = Index;
907 Op->RegIdx.RegInfo = RegInfo;
908 Op->RegIdx.Kind = RegKind;
909 Op->RegIdx.Tok.Data = Str.data();
910 Op->RegIdx.Tok.Length = Str.size();
911 Op->StartLoc = S;
912 Op->EndLoc = E;
923 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
931 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
939 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
949 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID)
957 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)
965 return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)
973 return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID)
984 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
992 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
1000 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
1008 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
1016 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
1024 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
1032 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
1040 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
1048 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
1056 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
1065 Inst.addOperand(MCOperand::createImm(CE->getValue()));
1149 // FIXME: We ought to do this for -integrated-as without -via-file-asm too.
1153 StartLoc, "-mno-odd-spreg prohibits the use of odd FPU "
1160 // FIXME: We ought to do this for -integrated-as without -via-file-asm too.
1162 AsmParser.Error(StartLoc, "-mno-odd-spreg prohibits the use of odd FPU "
1224 uint64_t Imm = getConstantImm() - Offset;
1225 Imm &= (1ULL << Bits) - 1;
1252 int64_t Imm = getConstantImm() - Offset;
1269 ? getMemBase()->getGPR64Reg()
1270 : getMemBase()->getGPR32Reg()));
1279 Inst.addOperand(MCOperand::createReg(getMemBase()->getGPRMM16Reg()));
1303 return isImm() && getImm()->evaluateAsAbsolute(Res);
1311 return isConstantImm() && isUInt<Bits>(getConstantImm() - Offset);
1329 return isConstantImm() && isInt<Bits>(getConstantImm() - Offset);
1354 if (!getMemBase()->isGPRAsmReg())
1361 bool IsReloc = getMemOff()->evaluateAsRelocatable(Res, nullptr, nullptr);
1368 if (!getMemBase()->isGPRAsmReg())
1375 bool IsReloc = getMemOff()->evaluateAsRelocatable(Res, nullptr, nullptr);
1380 return isMem() && getMemBase()->isMM16AsmReg();
1385 && getMemBase()->isRegIdx() && (getMemBase()->getGPR32Reg() == Mips::SP);
1390 && (getConstantMemOff() % 4 == 0) && getMemBase()->isRegIdx()
1391 && (getMemBase()->getGPR32Reg() == Mips::SP);
1396 && (getConstantMemOff() % 4 == 0) && getMemBase()->isRegIdx()
1397 && (getMemBase()->getGPR32Reg() == Mips::GP);
1416 bool Success = getImm()->evaluateAsRelocatable(Res, nullptr, nullptr);
1424 int Size = RegList.List->size();
1428 unsigned R0 = RegList.List->front();
1429 unsigned R1 = RegList.List->back();
1434 int PrevReg = *RegList.List->begin();
1435 for (int i = 1; i < Size - 1; i++) {
1480 (void)Val->evaluateAsAbsolute(Value);
1495 return static_cast<const MCConstantExpr *>(getMemOff())->getValue();
1506 Op->Tok.Data = Str.data();
1507 Op->Tok.Length = Str.size();
1508 Op->StartLoc = S;
1509 Op->EndLoc = S;
1581 Op->Imm.Val = Val;
1582 Op->StartLoc = S;
1583 Op->EndLoc = E;
1591 Op->Mem.Base = Base.release();
1592 Op->Mem.Off = Off;
1593 Op->StartLoc = S;
1594 Op->EndLoc = E;
1604 Op->RegList.List = new SmallVector<unsigned, 10>(Regs.begin(), Regs.end());
1605 Op->StartLoc = StartLoc;
1606 Op->EndLoc = EndLoc;
1659 // AFGR64 is $0-$15 but we handle this in getAFGR64()
1664 // AFGR64 is $0-$15 but we handle this in getAFGR64()
1706 /// getStartLoc - Get the location of the first token of this operand.
1708 /// getEndLoc - Get the location of the last token of this operand.
1720 Mem.Base->print(OS);
1784 return &SRExpr->getSymbol();
1788 const MCSymbol *LHSSym = getSingleMCSymbol(BExpr->getLHS());
1789 const MCSymbol *RHSSym = getSingleMCSymbol(BExpr->getRHS());
1801 return getSingleMCSymbol(UExpr->getSubExpr());
1811 return countMCSymbolRefExpr(BExpr->getLHS()) +
1812 countMCSymbolRefExpr(BExpr->getRHS());
1815 return countMCSymbolRefExpr(UExpr->getSubExpr());
1821 switch (Expr->getKind()) {
1825 return (cast<MCSymbolRefExpr>(Expr)->getKind() != MCSymbolRefExpr::VK_None);
1828 if (!isEvaluated(BE->getLHS()))
1830 return isEvaluated(BE->getRHS());
1833 return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr());
1845 const MCOperandInfo &OpInfo = MCID.operands()[NumOp - 1];
1851 MCOperand &Op = Inst.getOperand(NumOp - 1);
1861 if (Expr->getKind() != MCExpr::SymbolRef)
1866 return SR->getKind() == MCSymbolRefExpr::VK_None;
1877 const MCInstrDesc &MCID = MII.get(Opcode);
2026 Inst.getOperand(1).setImm(Imm - 32);
2047 // three operand instructions. The pre-R6 divide instructions however have
2108 // because the pseudo-instruction doesn't have a distinct opcode.
2159 switch (MCID.operands()[MCID.getNumOperands() - 1].OperandType) {
2173 // Try to create 16-bit GP relative load instruction.
2184 getContext().getRegisterInfo()->getRegClass(
2211 if (Imm < -1032 || Imm > 1028 || (Imm < 8 && Imm > -12) ||
2229 if (Imm < -1 || Imm > 126)
2237 if (!(Imm == 1 || Imm == -1 ||
2256 if (Imm < -1 || Imm > 14)
2321 MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder();
2343 if (AssemblerOptions.back()->isReorder() && !FillDelaySlot) {
2354 hasForbiddenSlot(MCID) && AssemblerOptions.back()->isReorder();
2378 AssemblerOptions.back()->isReorder()) {
2411 if (!AssemblerOptions.back()->isReorder())
2430 if (AssemblerOptions.back()->isReorder())
2703 // Create a JALR instruction which is going to replace the pseudo-JAL.
2736 const MCInstrDesc &MCID = MII.get(JalrInst.getOpcode());
2737 if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder())
2744 /// Can the value be represented by a unsigned N-bit value and a shift left?
2755 /// @param Is32BitImm Is ImmValue 32-bit or 64-bit?
2766 Error(IDLoc, "instruction requires a 64-bit architecture");
2772 // Sign extend up to 64-bit so that the predicates match the hardware
2777 Error(IDLoc, "instruction requires a 32-bit immediate");
2791 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) {
2846 // Expand to an ORi instead of a LUi to avoid sign-extending into the
2867 Error(IDLoc, "instruction requires a 32-bit immediate");
2872 // at least 17-bit wide here.
2874 assert(BitWidth >= 17 && "ImmValue must be at least 17-bit wide");
2878 unsigned ShiftAmount = BitWidth - 16;
2893 // The highest 32-bit's are equivalent to a 32-bit immediate load.
2895 // Load bits 32-63 of ImmValue into bits 0-31 of the temporary register.
2900 // Shift and accumulate into the register. If a 16-bit chunk is zero, then
2903 for (int BitNum = 16; BitNum >= 0; BitNum -= 16) {
2914 ShiftCarriedForwards -= 16;
2945 // la can't produce a usable address when addresses are 64-bit.
2947 Warning(IDLoc, "la used to load 64-bit address");
2952 // dla requires 64-bit addresses.
2954 Error(IDLoc, "instruction requires a 64-bit architecture");
2983 if (!SymExpr->evaluateAsRelocatable(Res, nullptr, nullptr)) {
2994 Res.getSymA()->getSymbol().isInSection() ||
2995 Res.getSymA()->getSymbol().isTemporary() ||
2996 (Res.getSymA()->getSymbol().isELF() &&
2997 cast<MCSymbolELF>(Res.getSymA()->getSymbol()).getBinding() ==
2999 // For O32, "$"-prefixed symbols are recognized as temporary while
3000 // .L-prefixed symbols are not (PrivateGlobalPrefix is "$"). Recognize ".L"
3002 if (ABI.IsO32() && Res.getSymA()->getSymbol().getName().starts_with(".L"))
3004 bool UseXGOT = STI->hasFeature(Mips::FeatureXGOT) && !IsLocalSym;
3009 // or R_MIPS_CALL16 instead of R_MIPS_GOT_DISP in 64-bit case.
3034 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg,
3100 // FIXME: The correct range is a 32-bit sign-extended number.
3101 if (Res.getConstant() < -0x8000 || Res.getConstant() > 0x7fff) {
3152 // This is the 64-bit symbol address expansion.
3154 // We need AT for the 64-bit expansion in the cases where the optional
3168 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg);
3251 "pseudo-instruction requires $at, which is not available");
3256 // And now, the 32-bit symbol address expansion:
3267 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) {
3284 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, TmpReg));
3289 // Each double-precision register DO-D15 overlaps with two of the single
3290 // precision registers F0-F31. As an example, all of the following hold true:
3381 // 64-bit addresses).
3382 // FIXME: With -msym32 option, the address expansion for N64 should probably
3641 assert(MII.get(Inst.getOpcode()).getNumOperands() == 1 &&
3655 // 16-bit unconditional branch instruction.
3674 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
3675 if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder())
3713 llvm_unreachable("Unknown immediate branch pseudo-instruction.");
3765 const MCInstrDesc &Desc = MII.get(OpCode);
3768 getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
3792 // HiOffset to account for the sign-extension of the low part.
3816 // do not exceed 16-bit.
3821 if (!OffsetOp.getExpr()->evaluateAsRelocatable(Res, nullptr, nullptr)) {
3834 // FIXME: Implement 64-bit case.
3892 const MCInstrDesc &Desc = MII.get(OpCode);
3895 getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
3939 assert(Inst.getOperand(OpNum - 1).isImm() &&
3940 Inst.getOperand(OpNum - 2).isReg() &&
3941 Inst.getOperand(OpNum - 3).isReg() && "Invalid instruction operand.");
3943 if (OpNum < 8 && Inst.getOperand(OpNum - 1).getImm() <= 60 &&
3944 Inst.getOperand(OpNum - 1).getImm() >= 0 &&
3945 (Inst.getOperand(OpNum - 2).getReg() == Mips::SP ||
3946 Inst.getOperand(OpNum - 2).getReg() == Mips::SP_64) &&
3947 (Inst.getOperand(OpNum - 3).getReg() == Mips::RA ||
3948 Inst.getOperand(OpNum - 3).getReg() == Mips::RA_64)) {
3987 llvm_unreachable("unknown opcode for branch pseudo-instruction");
4093 llvm_unreachable("unknown opcode for branch pseudo-instruction");
4099 // FIXME: All of these Opcode-specific if's are needed for compatibility
4130 // If both registers are $0 and the pseudo-branch accepts equality, it
4137 // If both registers are $0 and the pseudo-branch does not accept
4144 // If the $rs is $0 and the pseudo-branch is BGTU (0 > x) or
4145 // if the $rt is $0 and the pseudo-branch is BLTU (x < 0),
4146 // the pseudo-branch will never be taken, so we don't emit anything.
4147 // This only applies to unsigned pseudo-branches.
4152 // If the $rs is $0 and the pseudo-branch is BLEU (0 <= x) or
4153 // if the $rt is $0 and the pseudo-branch is BGEU (x >= 0),
4154 // the pseudo-branch will always be taken, so we emit an unconditional
4156 // This only applies to unsigned pseudo-branches.
4163 // If the $rs is $0 and the pseudo-branch is BLTU (0 < x) or
4164 // if the $rt is $0 and the pseudo-branch is BGTU (x > 0),
4165 // the pseudo-branch will be taken only when the non-zero register is
4168 // If the $rs is $0 and the pseudo-branch is BGEU (0 >= x) or
4169 // if the $rt is $0 and the pseudo-branch is BLEU (x <= 0),
4170 // the pseudo-branch will be taken only when the non-zero register is
4180 // If we have a signed pseudo-branch and one of the registers is $0,
4181 // we can use an appropriate compare-to-zero branch. We select which one
4198 // SLT fits well with 2 of our 4 pseudo-branches:
4199 // BLT, where $rs < $rt, translates into "slt $at, $rs, $rt" and
4200 // BGT, where $rs > $rt, translates into "slt $at, $rt, $rs".
4204 // The other 2 pseudo-branches are opposites of the above 2 (BGE with BLT
4226 // Notably we don't have to emit a warning when encountering $rt as the $zero
4298 if (isRem && (ImmValue == 1 || (Signed && (ImmValue == -1)))) {
4304 } else if (isDiv && Signed && ImmValue == -1) {
4372 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI);
5005 ShiftValue = MaxShift - ImmValue;
5042 TOut.emitRRI(SecondShift, DReg, SReg, 32 - ImmValue, Inst.getLoc(), STI);
5147 ShiftValue = (32 - ImmValue % 32) % 32;
5198 TOut.emitRRI(SecondShift, DReg, SReg, (32 - ImmValue % 32) % 32,
5278 if (AssemblerOptions.back()->isReorder())
5315 if (AssemblerOptions.back()->isReorder())
5482 if (Imm > -0x8000 && Imm < 0) {
5483 Imm = -Imm;
5564 if (ImmValue > -0x8000 && ImmValue < 0) {
5565 ImmValue = -ImmValue;
5855 // It also applies for registers Rt and Rs of microMIPSr6 jalrc.hb instruction
5883 // c) rs < rt for bnec, beqc.
5889 // would overflow must have rs >= rt. That can be handled like beqc/bnec with
5975 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
5987 SMLoc ErrorLoc = Operands[ErrorInfo]->getStartLoc();
6021 ErrorLoc = Operands[ErrorInfo]->getStartLoc();
6030 "s-type must be zero or unspecified for pre-MIPS32 ISAs");
6032 return Error(IDLoc, "selector must be zero for pre-MIPS32 ISAs");
6045 "non-zero fcc register doesn't exist in current ISA level");
6050 "expected 1-bit unsigned immediate");
6053 "expected 2-bit unsigned immediate");
6059 "expected 3-bit unsigned immediate");
6062 "expected 4-bit unsigned immediate");
6065 "expected 4-bit signed immediate");
6068 "expected 5-bit unsigned immediate");
6071 "expected 5-bit signed immediate");
6085 "expected 6-bit unsigned immediate");
6088 "expected both 7-bit unsigned immediate and multiple of 4");
6094 "expected 6-bit unsigned immediate");
6097 "expected both 8-bit unsigned immediate and multiple of 4");
6100 "expected 6-bit signed immediate");
6103 "expected 7-bit unsigned immediate");
6106 "expected immediate in range -1 .. 126");
6109 "expected both 9-bit signed immediate and multiple of 4");
6112 "expected 8-bit unsigned immediate");
6115 "expected 10-bit unsigned immediate");
6118 "expected 10-bit signed immediate");
6121 "expected 11-bit signed immediate");
6126 "expected 16-bit unsigned immediate");
6130 "expected 16-bit signed immediate");
6133 "expected both 19-bit signed immediate and multiple of 4");
6136 "expected 20-bit unsigned immediate");
6139 "expected 26-bit unsigned immediate");
6143 "expected 32-bit signed immediate");
6146 "expected 32-bit immediate");
6149 "expected memory with 9-bit signed offset");
6152 "expected memory with 10-bit signed offset");
6155 "expected memory with 11-bit signed offset and multiple of 2");
6158 "expected memory with 12-bit signed offset and multiple of 4");
6161 "expected memory with 13-bit signed offset and multiple of 8");
6164 "expected memory with 11-bit signed offset");
6167 "expected memory with 12-bit signed offset");
6170 "expected memory with 16-bit signed offset");
6173 "expected memory with 32-bit signed offset");
6175 SMLoc ErrorStart = Operands[3]->getStartLoc();
6176 SMLoc ErrorEnd = Operands[4]->getEndLoc();
6181 SMLoc ErrorStart = Operands[3]->getStartLoc();
6182 SMLoc ErrorEnd = Operands[4]->getEndLoc();
6187 SMLoc ErrorStart = Operands[3]->getStartLoc();
6188 SMLoc ErrorEnd = Operands[4]->getEndLoc();
6198 if (RegIndex != 0 && AssemblerOptions.back()->getATRegIndex() == RegIndex)
6204 if (!AssemblerOptions.back()->isMacro())
6264 .Default(-1);
6270 // Name is one of t4-t7
6280 assert(FixedName != "" && "Register name is not one of t4-t7.");
6282 printWarningWithFixIt("register names $t4-$t7 are only available in O32.",
6286 // Although SGI documentation just cuts out t0-t3 for n32/n64,
6287 // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7
6288 // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7.
6292 if (CC == -1)
6300 .Default(-1);
6314 .Default(-1);
6324 return -1; // This is not an integer.
6326 return -1;
6329 return -1;
6337 return -1; // This is not an integer.
6339 return -1;
6342 return -1;
6350 return -1; // This is not an integer.
6352 return -1;
6355 return -1;
6362 return -1;
6365 return -1;
6382 .Default(-1);
6388 return AssemblerOptions.back()->getATRegIndex() != 0;
6392 unsigned ATIndex = AssemblerOptions.back()->getATRegIndex();
6395 "pseudo-instruction requires $at, which is not available");
6404 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
6442 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6459 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6492 return (Reg == (unsigned)-1) ? ParseStatus::NoMatch : ParseStatus::Success;
6496 return (Reg == (unsigned)-1) ? ParseStatus::NoMatch : ParseStatus::Success;
6531 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6537 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6548 // GAS and LLVM treat comparison operators different. GAS will generate -1
6612 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6628 if (IdVal->evaluateAsAbsolute(Imm))
6630 else if (BE->getLHS()->getKind() != MCExpr::SymbolRef)
6631 IdVal = MCBinaryExpr::create(BE->getOpcode(), BE->getRHS(), BE->getLHS(),
6646 if (Sym->isVariable()) {
6647 const MCExpr *Expr = Sym->getVariableValue();
6648 if (Expr->getKind() == MCExpr::SymbolRef) {
6650 StringRef DefSymbol = Ref->getSymbol().getName();
6662 } else if (Sym->isUnset()) {
6666 auto Entry = RegisterSets.find(Sym->getName());
6669 matchAnyRegisterWithoutDollar(Operands, Entry->getValue(), S);
6683 if (Index != -1) {
6691 if (Index != -1) {
6699 if (Index != -1) {
6707 if (Index != -1) {
6715 if (Index != -1) {
6723 if (Index != -1) {
6731 if (Index != -1) {
6784 LLVM_DEBUG(dbgs() << ".. !$ -> try sym aliasing\n");
6789 LLVM_DEBUG(dbgs() << ".. !symalias -> NoMatch\n");
6833 return matchCPURegisterName(Parser.getLexer().peekTok().getString()) == -1
6842 int64_t Val = MCE->getValue();
6843 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
6845 MCConstantExpr::create(0 - Val, getContext()), S, E, *this));
6910 return Error(E, "',' or '-' expected");
6984 // This target-overriden function exists to maintain current behaviour for
7063 AssemblerOptions.back()->setATRegIndex(0);
7086 AssemblerOptions.back()->setATRegIndex(1);
7123 if (!AssemblerOptions.back()->setATRegIndex(AtRegNo)) {
7149 AssemblerOptions.back()->setReorder();
7163 AssemblerOptions.back()->setNoReorder();
7177 AssemblerOptions.back()->setMacro();
7191 if (AssemblerOptions.back()->isReorder()) {
7195 AssemblerOptions.back()->setNoMacro();
7444 ComputeAvailableFeatures(AssemblerOptions.back()->getFeatures()));
7445 STI.setFeatureBits(AssemblerOptions.back()->getFeatures());
7471 setFeatureBits(Mips::FeatureSoftFloat, "soft-float");
7482 clearFeatureBits(Mips::FeatureSoftFloat, "soft-float");
7514 Sym->setVariableValue(Value);
7528 ComputeAvailableFeatures(AssemblerOptions.front()->getFeatures()));
7529 STI.setFeatureBits(AssemblerOptions.front()->getFeatures());
7530 AssemblerOptions.back()->setFeatures(AssemblerOptions.front()->getFeatures());
7726 if (AssemblerOptions.back()->isReorder())
7795 // is used in non-PIC mode.
7810 if (!StackOffset->evaluateAsAbsolute(StackOffsetVal)) {
7868 !OffsetExpr->evaluateAsAbsolute(OffsetVal)) {
7893 if (Expr->getKind() != MCExpr::SymbolRef) {
7902 getTargetStreamer().emitDirectiveCpsetup(FuncReg, Save, Ref->getSymbol(),
8346 setModuleFeatureBits(Mips::FeatureSoftFloat, "soft-float");
8365 clearModuleFeatureBits(Mips::FeatureSoftFloat, "soft-float");
8678 // we still give helpful extension-related error messages.
8683 if (!DummyNumber->evaluateAsAbsolute(DummyNumberVal)) {
8721 if ((SymbolName != CurrentFn->getName())) {
8765 if (!FrameSize->evaluateAsAbsolute(FrameSizeVal)) {
8815 // .mask 0x80000000, -4
8816 // .fmask 0x80000000, -4
8828 if (!BitMask->evaluateAsAbsolute(BitMaskVal)) {
8849 if (!FrameOffset->evaluateAsAbsolute(FrameOffsetVal)) {