Lines Matching defs:DstRegOp

2930   const MCOperand &DstRegOp = Inst.getOperand(0);
2931   assert(DstRegOp.isReg() && "expected register operand kind");
2933   if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
3684   const MCOperand &DstRegOp = Inst.getOperand(0);
3685   assert(DstRegOp.isReg() && "expected register operand kind");
3720       TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO,
3724       TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc,
3738       TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg,
3742       TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, STI);
3753   const MCOperand &DstRegOp = Inst.getOperand(StartOp);
3754   assert(DstRegOp.isReg() && "expected register operand kind");
3761   unsigned DstReg = DstRegOp.getReg();
3880   const MCOperand &DstRegOp = Inst.getOperand(StartOp);
3881   assert(DstRegOp.isReg() && "expected register operand kind");
3888   unsigned DstReg = DstRegOp.getReg();
4448   const MCOperand &DstRegOp = Inst.getOperand(0);
4449   assert(DstRegOp.isReg() && "expected register operand kind");
4456   unsigned DstReg = DstRegOp.getReg();
4500   const MCOperand &DstRegOp = Inst.getOperand(0);
4501   assert(DstRegOp.isReg() && "expected register operand kind");
4508   unsigned DstReg = DstRegOp.getReg();
4551   const MCOperand &DstRegOp = Inst.getOperand(0);
4552   assert(DstRegOp.isReg() && "expected register operand kind");
4559   unsigned DstReg = DstRegOp.getReg();